From patchwork Mon Mar 9 03:45:01 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 243410 List-Id: U-Boot discussion From: sjg at chromium.org (Simon Glass) Date: Sun, 8 Mar 2020 21:45:01 -0600 Subject: [PATCH v2 37/39] x86: Allow devices to write an SSDT In-Reply-To: <20200309034504.149659-1-sjg@chromium.org> References: <20200309034504.149659-1-sjg@chromium.org> Message-ID: <20200308214442.v2.37.Id6fc7367886ec2e2d9f2ddf423ad32720e14e5e5@changeid> Call the new core function to write the SSDT. This is made up of fragments generated by devices that have the fill_ssdt() method. Signed-off-by: Simon Glass --- Changes in v2: - Move ACPI_TABLE_CREATOR to here arch/x86/lib/acpi_table.c | 50 +++++++++++++++++++++++++++++++++++++++ include/acpi_table.h | 1 + 2 files changed, 51 insertions(+) diff --git a/arch/x86/lib/acpi_table.c b/arch/x86/lib/acpi_table.c index 694e92c158..3b97fe162c 100644 --- a/arch/x86/lib/acpi_table.c +++ b/arch/x86/lib/acpi_table.c @@ -7,6 +7,7 @@ */ #include +#include #include #include #include @@ -344,6 +345,46 @@ static void acpi_create_spcr(struct acpi_spcr *spcr) header->checksum = table_compute_checksum((void *)spcr, header->length); } +static void acpi_ssdt_write_cbtable(struct acpi_ctx *ctx) +{ + uintptr_t base; + u32 size; + + base = 0; + size = 0; + + acpigen_write_device(ctx, "CTBL"); + acpigen_write_coreboot_hid(ctx, COREBOOT_ACPI_ID_CBTABLE); + acpigen_write_name_integer(ctx, "_UID", 0); + acpigen_write_sta(ctx, ACPI_STATUS_DEVICE_HIDDEN_ON); + acpigen_write_name(ctx, "_CRS"); + acpigen_write_resourcetemplate_header(ctx); + acpigen_write_mem32fixed(ctx, 0, base, size); + acpigen_write_resourcetemplate_footer(ctx); + acpigen_pop_len(ctx); +} + +void acpi_create_ssdt(struct acpi_ctx *ctx, struct acpi_table_header *ssdt, + const char *oem_table_id) +{ + memset((void *)ssdt, '\0', sizeof(struct acpi_table_header)); + + acpi_fill_header(ssdt, "SSDT"); + ssdt->revision = acpi_get_table_revision(ACPITAB_SSDT); + ssdt->aslc_revision = 1; + ssdt->length = sizeof(struct acpi_table_header); + + acpi_inc(ctx, sizeof(struct acpi_table_header)); + + /* Write object to declare coreboot tables */ + acpi_ssdt_write_cbtable(ctx); + acpi_fill_ssdt(ctx); + + /* (Re)calculate length and checksum. */ + ssdt->length = ctx->current - (void *)ssdt; + ssdt->checksum = table_compute_checksum((void *)ssdt, ssdt->length); +} + /* * QEMU's version of write_acpi_tables is defined in drivers/misc/qfw.c */ @@ -353,6 +394,7 @@ ulong write_acpi_tables(ulong start_addr) struct acpi_facs *facs; struct acpi_table_header *dsdt; struct acpi_fadt *fadt; + struct acpi_table_header *ssdt; struct acpi_mcfg *mcfg; struct acpi_madt *madt; struct acpi_csrt *csrt; @@ -408,6 +450,14 @@ ulong write_acpi_tables(ulong start_addr) acpi_create_fadt(fadt, facs, dsdt); acpi_add_table(ctx, fadt); + debug("ACPI: * SSDT\n"); + ssdt = (struct acpi_table_header *)ctx->current; + acpi_create_ssdt(ctx, ssdt, ACPI_TABLE_CREATOR); + if (ssdt->length > sizeof(struct acpi_table_header)) { + acpi_inc_align(ctx, ssdt->length); + acpi_add_table(ctx, ssdt); + } + debug("ACPI: * MCFG\n"); mcfg = ctx->current; acpi_create_mcfg(mcfg); diff --git a/include/acpi_table.h b/include/acpi_table.h index 5fd2cef5d1..2a802758aa 100644 --- a/include/acpi_table.h +++ b/include/acpi_table.h @@ -17,6 +17,7 @@ #define OEM_ID "U-BOOT" /* U-Boot */ #define OEM_TABLE_ID "U-BOOTBL" /* U-Boot Table */ #define ASLC_ID "INTL" /* Intel ASL Compiler */ +#define ACPI_TABLE_CREATOR OEM_TABLE_ID #define ACPI_RSDP_REV_ACPI_1_0 0 #define ACPI_RSDP_REV_ACPI_2_0 2