From patchwork Fri Mar 6 08:55:19 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Tan, Ley Foon" X-Patchwork-Id: 243280 List-Id: U-Boot discussion From: ley.foon.tan at intel.com (Ley Foon Tan) Date: Fri, 6 Mar 2020 16:55:19 +0800 Subject: [PATCH v2 2/3] configs: socfpga: Change to use SOCFPGA_PHYS_OCRAM_SIZE macro In-Reply-To: <20200306085520.4751-1-ley.foon.tan@intel.com> References: <20200306085520.4751-1-ley.foon.tan@intel.com> Message-ID: <20200306085520.4751-3-ley.foon.tan@intel.com> Change to use SOCFPGA_PHYS_OCRAM_SIZE macro for onchip RAM size. Signed-off-by: Ley Foon Tan --- include/configs/socfpga_common.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index ec4184369539..410ec80618f5 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -21,14 +21,15 @@ #define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1_SIZE #if defined(CONFIG_TARGET_SOCFPGA_GEN5) #define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x10000 +#define CONFIG_SYS_INIT_RAM_SIZE SOCFPGA_PHYS_OCRAM_SIZE #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) #define CONFIG_SYS_INIT_RAM_ADDR 0xFFE00000 /* SPL memory allocation configuration, this is for FAT implementation */ #ifndef CONFIG_SYS_SPL_MALLOC_SIZE #define CONFIG_SYS_SPL_MALLOC_SIZE 0x10000 #endif -#define CONFIG_SYS_INIT_RAM_SIZE (0x40000 - CONFIG_SYS_SPL_MALLOC_SIZE) +#define CONFIG_SYS_INIT_RAM_SIZE (SOCFPGA_PHYS_OCRAM_SIZE - \ + CONFIG_SYS_SPL_MALLOC_SIZE) #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_INIT_RAM_ADDR + \ CONFIG_SYS_INIT_RAM_SIZE) #endif