From patchwork Fri Mar 6 08:55:18 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Tan, Ley Foon" X-Patchwork-Id: 243278 List-Id: U-Boot discussion From: ley.foon.tan at intel.com (Ley Foon Tan) Date: Fri, 6 Mar 2020 16:55:18 +0800 Subject: [PATCH v2 1/3] arm: socfpga: Add onchip RAM size macro In-Reply-To: <20200306085520.4751-1-ley.foon.tan@intel.com> References: <20200306085520.4751-1-ley.foon.tan@intel.com> Message-ID: <20200306085520.4751-2-ley.foon.tan@intel.com> Add OCRAM size macro for Gen5 and Arria 10. Signed-off-by: Ley Foon Tan --- arch/arm/mach-socfpga/include/mach/base_addr_a10.h | 2 ++ arch/arm/mach-socfpga/include/mach/base_addr_ac5.h | 2 ++ 2 files changed, 4 insertions(+) diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_a10.h b/arch/arm/mach-socfpga/include/mach/base_addr_a10.h index 929c413e0392..b947cc07291c 100644 --- a/arch/arm/mach-socfpga/include/mach/base_addr_a10.h +++ b/arch/arm/mach-socfpga/include/mach/base_addr_a10.h @@ -47,4 +47,6 @@ #define SOCFPGA_SDR_FIREWALL_L3_ADDRESS 0xffd13400 #define SOCFPGA_NOC_FW_H2F_SCR_OFST 0xffd13500 +#define SOCFPGA_PHYS_OCRAM_SIZE 0x40000 + #endif /* _SOCFPGA_A10_BASE_HARDWARE_H_ */ diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_ac5.h b/arch/arm/mach-socfpga/include/mach/base_addr_ac5.h index 2725e9fcc345..da966fb45836 100644 --- a/arch/arm/mach-socfpga/include/mach/base_addr_ac5.h +++ b/arch/arm/mach-socfpga/include/mach/base_addr_ac5.h @@ -59,4 +59,6 @@ #define SOCFPGA_DMANONSECURE_ADDRESS 0xffe00000 #define SOCFPGA_DMASECURE_ADDRESS 0xffe01000 +#define SOCFPGA_PHYS_OCRAM_SIZE 0x10000 + #endif /* _SOCFPGA_BASE_ADDRS_H_ */