From patchwork Wed Feb 26 12:56:06 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pratyush Yadav X-Patchwork-Id: 236874 List-Id: U-Boot discussion From: p.yadav at ti.com (Pratyush Yadav) Date: Wed, 26 Feb 2020 18:26:06 +0530 Subject: [NOT FOR MERGE PATCH 16/15] arm: dts: k3-j721e: Update OSPI settings for octal DTR mode In-Reply-To: <20200226125606.22684-1-p.yadav@ti.com> References: <20200226125606.22684-1-p.yadav@ti.com> Message-ID: <20200226125606.22684-17-p.yadav@ti.com> The Cypress Semper flash supports octal DTR mode, so update the device tree settings to use 8 data lines for both Rx and Tx and allow using DTR mode on both lines. The read delay is set to 4. The calibration sequence yields a value of 2 but since the sequence is run before the flash is switched to octal DTR mode, it gets that value for legacy mode. In octal DTR mode the flash needs a read delay of 4. Setting read delay here over-rides the calibrated value. Signed-off-by: Pratyush Yadav --- These are the DT changes made on top of u-boot-ti/next to test these changes. arch/arm/dts/k3-j721e-som-p0.dtsi | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) -- 2.25.0 diff --git a/arch/arm/dts/k3-j721e-som-p0.dtsi b/arch/arm/dts/k3-j721e-som-p0.dtsi index 8497ff3e3e..3e5fefd426 100644 --- a/arch/arm/dts/k3-j721e-som-p0.dtsi +++ b/arch/arm/dts/k3-j721e-som-p0.dtsi @@ -85,14 +85,16 @@ flash at 0{ compatible = "jedec,spi-nor"; reg = <0x0>; - spi-tx-bus-width = <1>; + spi-tx-bus-width = <8>; spi-rx-bus-width = <8>; - spi-max-frequency = <40000000>; + spi-tx-dtr = <1>; + spi-rx-dtr = <1>; + spi-max-frequency = <25000000>; cdns,tshsl-ns = <60>; cdns,tsd2d-ns = <60>; cdns,tchsh-ns = <60>; cdns,tslch-ns = <60>; - cdns,read-delay = <0>; + cdns,read-delay = <4>; #address-cells = <1>; #size-cells = <1>; };