diff mbox series

[3/3] clk: imx6: Add definition for IMX6QDL_CLK_ENET_REF clock

Message ID 20200224135526.25534-4-lukma@denx.de
State Accepted
Commit 32f462ba3bf0c8794653e6ff92ca5cbec9856c54
Headers show
Series clk: Fix ETH initialization on i.MX6Q boards using CCF | expand

Commit Message

Lukasz Majewski Feb. 24, 2020, 1:55 p.m. UTC 
After commit 673f6597321d ("net: fec_mxc: support i.MX8M with CLK_CCF") all
NXP boards, which are not IMX8 and in the same time are supporting CCF need
to provide PTP clock.

On the i.MX6Q this clock is provided with IMX6QDL_CLK_ENET_REF in the Linux
kernel's CCF.

Code in this change models the simplest case when enet reference clock is
generated from 'osc' clock.

Signed-off-by: Lukasz Majewski <lukma at denx.de>
---

 drivers/clk/imx/clk-imx6q.c | 7 +++++++
 1 file changed, 7 insertions(+)
diff mbox series

Patch

diff --git a/drivers/clk/imx/clk-imx6q.c b/drivers/clk/imx/clk-imx6q.c
index ace60ecec6..0f4c1f881d 100644
--- a/drivers/clk/imx/clk-imx6q.c
+++ b/drivers/clk/imx/clk-imx6q.c
@@ -112,6 +112,10 @@  static int imx6q_clk_probe(struct udevice *dev)
 	       imx_clk_pfd("pll2_pfd0_352m", "pll2_bus", base + 0x100, 0));
 	clk_dm(IMX6QDL_CLK_PLL2_PFD2_396M,
 	       imx_clk_pfd("pll2_pfd2_396m", "pll2_bus", base + 0x100, 2));
+	clk_dm(IMX6QDL_CLK_PLL6,
+	       imx_clk_pllv3(IMX_PLLV3_ENET, "pll6", "osc", base + 0xe0, 0x3));
+	clk_dm(IMX6QDL_CLK_PLL6_ENET,
+	       imx_clk_gate("pll6_enet", "pll6", base + 0xe0, 13));
 
 	/* CCM clocks */
 	base = dev_read_addr_ptr(dev);
@@ -183,6 +187,9 @@  static int imx6q_clk_probe(struct udevice *dev)
 	       imx_clk_gate2("i2c2", "ipg_per", base + 0x70, 8));
 
 	clk_dm(IMX6QDL_CLK_ENET, imx_clk_gate2("enet", "ipg", base + 0x6c, 10));
+	clk_dm(IMX6QDL_CLK_ENET_REF,
+	       imx_clk_fixed_factor("enet_ref", "pll6_enet", 1, 1));
+
 	return 0;
 }