diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 89b93e5de2..c4a9a9f624 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -910,4 +910,37 @@ config X86_OFFSET_SPL
 	depends on SPL && X86
 	default SPL_TEXT_BASE
 
+config ACPI_GPE
+	bool "Support ACPI general-purpose events"
+	help
+	  Enable a driver for ACPI GPEs to allow peripherals to send interrupts
+	  via ACPI to the OS. In U-Boot this is only used when U-Boot itself
+	  needs access to these interrupts. This can happen when it uses a
+	  peripheral that is set up to use GPEs and so cannot use the normal
+	  GPIO mechanism for polling an input.
+
+	  See https://queue.acm.org/blogposting.cfm?id=18977 for more info
+
+config SPL_ACPI_GPE
+	bool "Support ACPI general-purpose events in SPL"
+	help
+	  Enable a driver for ACPI GPEs to allow peripherals to send interrupts
+	  via ACPI to the OS. In U-Boot this is only used when U-Boot itself
+	  needs access to these interrupts. This can happen when it uses a
+	  peripheral that is set up to use GPEs and so cannot use the normal
+	  GPIO mechanism for polling an input.
+
+	  See https://queue.acm.org/blogposting.cfm?id=18977 for more info
+
+config TPL_ACPI_GPE
+	bool "Support ACPI general-purpose events in TPL"
+	help
+	  Enable a driver for ACPI GPEs to allow peripherals to send interrupts
+	  via ACPI to the OS. In U-Boot this is only used when U-Boot itself
+	  needs access to these interrupts. This can happen when it uses a
+	  peripheral that is set up to use GPEs and so cannot use the normal
+	  GPIO mechanism for polling an input.
+
+	  See https://queue.acm.org/blogposting.cfm?id=18977 for more info
+
 endmenu
diff --git a/arch/x86/cpu/Makefile b/arch/x86/cpu/Makefile
index 5b40838e60..307267a8fb 100644
--- a/arch/x86/cpu/Makefile
+++ b/arch/x86/cpu/Makefile
@@ -55,6 +55,7 @@ obj-$(CONFIG_INTEL_QUEENSBAY) += queensbay/
 obj-$(CONFIG_INTEL_TANGIER) += tangier/
 obj-$(CONFIG_APIC) += lapic.o ioapic.o
 obj-$(CONFIG_$(SPL_TPL_)X86_32BIT_INIT) += irq.o
+obj-$(CONFIG_$(SPL_TPL_)ACPI_GPE) += acpi_gpe.o
 obj-$(CONFIG_QFW) += qfw_cpu.o
 ifndef CONFIG_$(SPL_)X86_64
 obj-$(CONFIG_SMP) += mp_init.o
diff --git a/arch/x86/cpu/acpi_gpe.c b/arch/x86/cpu/acpi_gpe.c
new file mode 100644
index 0000000000..55005455c0
--- /dev/null
+++ b/arch/x86/cpu/acpi_gpe.c
@@ -0,0 +1,85 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 Google, LLC
+ * Written by Simon Glass <sjg at chromium.org>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <irq.h>
+#include <asm/io.h>
+
+/**
+ * struct acpi_gpe_priv - private driver information
+ *
+ * @acpi_base: Base I/O address of ACPI registers
+ */
+struct acpi_gpe_priv {
+	ulong acpi_base;
+};
+
+#define GPE0_STS(x)		(0x20 + ((x) * 4))
+
+static int acpi_gpe_read_and_clear(struct irq *irq)
+{
+	struct acpi_gpe_priv *priv = dev_get_priv(irq->dev);
+	u32 mask, sts;
+	ulong start;
+	int ret = 0;
+	int bank;
+
+	bank = irq->id / 32;
+	mask = 1 << (irq->id % 32);
+
+	/* Wait up to 1ms for GPE status to clear */
+	start = get_timer(0);
+	do {
+		if (get_timer(start) > 1)
+			return ret;
+
+		sts = inl(priv->acpi_base + GPE0_STS(bank));
+		if (sts & mask) {
+			outl(mask, priv->acpi_base + GPE0_STS(bank));
+			ret = 1;
+		}
+	} while (sts & mask);
+
+	return ret;
+}
+
+static int acpi_gpe_ofdata_to_platdata(struct udevice *dev)
+{
+	struct acpi_gpe_priv *priv = dev_get_priv(dev);
+
+	priv->acpi_base = dev_read_addr(dev);
+	if (!priv->acpi_base || priv->acpi_base == FDT_ADDR_T_NONE)
+		return log_msg_ret("acpi_base", -EINVAL);
+
+	return 0;
+}
+
+static int acpi_gpe_of_xlate(struct irq *irq, struct ofnode_phandle_args *args)
+{
+	irq->id = args->args[0];
+
+	return 0;
+}
+
+static const struct irq_ops acpi_gpe_ops = {
+	.read_and_clear		= acpi_gpe_read_and_clear,
+	.of_xlate		= acpi_gpe_of_xlate,
+};
+
+static const struct udevice_id acpi_gpe_ids[] = {
+	{ .compatible = "intel,acpi-gpe", .data = X86_IRQT_ACPI_GPE },
+	{ }
+};
+
+U_BOOT_DRIVER(acpi_gpe_drv) = {
+	.name		= "acpi_gpe",
+	.id		= UCLASS_IRQ,
+	.of_match	= acpi_gpe_ids,
+	.ops		= &acpi_gpe_ops,
+	.ofdata_to_platdata	= acpi_gpe_ofdata_to_platdata,
+	.priv_auto_alloc_size = sizeof(struct acpi_gpe_priv),
+};
diff --git a/doc/device-tree-bindings/interrupt-controller/intel,acpi-gpe.txt b/doc/device-tree-bindings/interrupt-controller/intel,acpi-gpe.txt
new file mode 100644
index 0000000000..d9252bf29f
--- /dev/null
+++ b/doc/device-tree-bindings/interrupt-controller/intel,acpi-gpe.txt
@@ -0,0 +1,30 @@
+* Intel Advanced Configuration and Power Interface General Purpose Events
+
+This describes an interrupt controller which provides access to GPEs supported
+by the SoC.
+
+Required properties:
+
+- compatible : "intel,acpi-gpe"
+- interrupt-controller : Identifies the node as an interrupt controller
+- #interrupt-cells : The number of cells to define the interrupts.  Must be 2:
+     cell 0: interrupt number (normally >=32 since GPEs below that are reserved)
+     cell 1: 0 (flags, but none are currently defined)
+- reg : The register bank for the controller (set this to the ACPI base).
+
+Example:
+
+	general-purpose-events {
+		reg = <IOMAP_ACPI_BASE IOMAP_ACPI_SIZE>;
+		compatible = "intel,acpi-gpe";
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	...
+	tpm at 50 {
+		reg = <0x50>;
+		compatible = "google,cr50";
+		ready-gpio = <&gpio_n 0x1c GPIO_ACTIVE_LOW>;
+		interrupts-extended = <&acpi_gpe 0x3c 0>;
+	};
