From patchwork Wed Jan 29 12:18:48 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vignesh Raghavendra X-Patchwork-Id: 240445 List-Id: U-Boot discussion From: vigneshr at ti.com (Vignesh Raghavendra) Date: Wed, 29 Jan 2020 17:48:48 +0530 Subject: [PATCH 2/9] ARM: mach-k3: arm64-mmu: map 64bit FSS MMIO space in A53 MMU In-Reply-To: <20200129121855.30112-1-vigneshr@ti.com> References: <20200129121855.30112-1-vigneshr@ti.com> Message-ID: <20200129121855.30112-3-vigneshr@ti.com> Populate address mapping entries in A53 MMU for 4 GB of MMIO space reserved for providing MMIO access to multiple flash devices through OSPI/HBMC IPs within FSS. Signed-off-by: Vignesh Raghavendra --- arch/arm/mach-k3/arm64-mmu.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/mach-k3/arm64-mmu.c b/arch/arm/mach-k3/arm64-mmu.c index 7f908eee803b..b1d1d6e494fc 100644 --- a/arch/arm/mach-k3/arm64-mmu.c +++ b/arch/arm/mach-k3/arm64-mmu.c @@ -49,6 +49,13 @@ struct mm_region am654_mem_map[NR_MMU_REGIONS] = { .size = 0x80000000UL, .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE + }, { + .virt = 0x500000000UL, + .phys = 0x500000000UL, + .size = 0x400000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN }, { /* List terminator */ 0,