From patchwork Mon Jan 27 12:29:25 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vignesh Raghavendra X-Patchwork-Id: 240280 List-Id: U-Boot discussion From: vigneshr at ti.com (Vignesh Raghavendra) Date: Mon, 27 Jan 2020 17:59:25 +0530 Subject: [PATCH 3/7] arm: dts: k3-j721e-common-proc-board: Enable USB0 in peripheral mode In-Reply-To: <20200127122929.25179-1-vigneshr@ti.com> References: <20200127122929.25179-1-vigneshr@ti.com> Message-ID: <20200127122929.25179-4-vigneshr@ti.com> Enable USB0 in peripheral mode so that it be used for DFU Signed-off-by: Vignesh Raghavendra --- arch/arm/dts/k3-j721e-r5-common-proc-board.dts | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm/dts/k3-j721e-r5-common-proc-board.dts b/arch/arm/dts/k3-j721e-r5-common-proc-board.dts index 28a355d49c9b..585cc839632b 100644 --- a/arch/arm/dts/k3-j721e-r5-common-proc-board.dts +++ b/arch/arm/dts/k3-j721e-r5-common-proc-board.dts @@ -40,6 +40,13 @@ clock-frequency = <200000000>; u-boot,dm-spl; }; + + clk_19_2mhz: dummy_clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <19200000>; + u-boot,dm-spl; + }; }; &cbass_mcu_wakeup { @@ -207,4 +214,15 @@ u-boot,dm-spl; }; +&usbss0 { + /delete-property/ power-domains; + /delete-property/ assigned-clocks; + /delete-property/ assigned-clock-parents; + clocks = <&clk_19_2mhz>; + clock-names = "usb2_refclk"; + pinctrl-names = "default"; + pinctrl-0 = <&main_usbss0_pins_default>; + ti,vbus-divider; +}; + #include "k3-j721e-common-proc-board-u-boot.dtsi"