From patchwork Mon Jan 27 05:06:33 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 240236 List-Id: U-Boot discussion From: sjg at chromium.org (Simon Glass) Date: Sun, 26 Jan 2020 22:06:33 -0700 Subject: [PATCH 086/108] x86: Support Atom SoCs using SWSMISCI rather than the SWSCI In-Reply-To: <20200127050655.170614-1-sjg@chromium.org> References: <20200127050655.170614-1-sjg@chromium.org> Message-ID: <20200126220508.86.I50851bb823bec6a8e470befd7d68f5a6ca7b7b4e@changeid> Some Atom SoCs use SWSMISCI for SMI control. Add a Kconfig to select this. It is used on Apollo Lake. Signed-off-by: Simon Glass --- arch/x86/Kconfig | 6 ++++++ arch/x86/cpu/apollolake/Kconfig | 1 + 2 files changed, 7 insertions(+) diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 61b6b48b81..930efc66cf 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -984,4 +984,10 @@ config INTEL_GENERIC_WIFI network functionality. It is only here to generate the ACPI tables required by Linux. +config INTEL_GMA_SWSMISCI + bool + help + Select this option for Atom-based platforms which use the SWSMISCI + register (0xe0) rather than the SWSCI register (0xe8). + endmenu diff --git a/arch/x86/cpu/apollolake/Kconfig b/arch/x86/cpu/apollolake/Kconfig index 6c62da04f0..e8a9a75112 100644 --- a/arch/x86/cpu/apollolake/Kconfig +++ b/arch/x86/cpu/apollolake/Kconfig @@ -16,6 +16,7 @@ config INTEL_APOLLOLAKE select PCIEX_LENGTH_256MB select PCH_SUPPORT select P2SB + select INTEL_GMA_SWSMISCI select ACPI_GNVS_EXTERNAL imply ENABLE_MRC_CACHE imply AHCI_PCI