From patchwork Mon Jan 27 05:06:25 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 240229 List-Id: U-Boot discussion From: sjg at chromium.org (Simon Glass) Date: Sun, 26 Jan 2020 22:06:25 -0700 Subject: [PATCH 078/108] x86: apl: Add power-management definitions In-Reply-To: <20200127050655.170614-1-sjg@chromium.org> References: <20200127050655.170614-1-sjg@chromium.org> Message-ID: <20200126220508.78.Iee393a0fe215071fcdbf17b373ed3b54a881a4fa@changeid> Add SCI and power-state definitions required by ACPI tables. Update the guard on acpi_pmc.h to avoid an error when buiding ASL. Signed-off-by: Simon Glass --- arch/x86/include/asm/arch-apollolake/pm.h | 56 +++++++++++++++++++---- include/power/acpi_pmc.h | 4 +- 2 files changed, 49 insertions(+), 11 deletions(-) diff --git a/arch/x86/include/asm/arch-apollolake/pm.h b/arch/x86/include/asm/arch-apollolake/pm.h index 6718290c4f..b63d60cd69 100644 --- a/arch/x86/include/asm/arch-apollolake/pm.h +++ b/arch/x86/include/asm/arch-apollolake/pm.h @@ -1,19 +1,57 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright (C) 2015-2016 Intel Corp. * (Written by Lance Zhao for Intel Corp.) + * Copyright 2019 Google LLC */ #ifndef _ASM_ARCH_PM_H #define _ASM_ARCH_PM_H -#define PMC_GPE_SW_31_0 0 -#define PMC_GPE_SW_63_32 1 -#define PMC_GPE_NW_31_0 3 -#define PMC_GPE_NW_63_32 4 -#define PMC_GPE_NW_95_64 5 -#define PMC_GPE_N_31_0 6 -#define PMC_GPE_N_63_32 7 -#define PMC_GPE_W_31_0 9 +#include + +#define PMC_GPE_SW_31_0 0 +#define PMC_GPE_SW_63_32 1 +#define PMC_GPE_NW_31_0 3 +#define PMC_GPE_NW_63_32 4 +#define PMC_GPE_NW_95_64 5 +#define PMC_GPE_N_31_0 6 +#define PMC_GPE_N_63_32 7 +#define PMC_GPE_W_31_0 9 + +#define IRQ_REG 0x106C +#define SCI_IRQ_ADJUST 24 +#define SCI_IRQ_SEL (255 << SCI_IRQ_ADJUST) +#define SCIS_IRQ9 9 +#define SCIS_IRQ10 10 +#define SCIS_IRQ11 11 +#define SCIS_IRQ20 20 +#define SCIS_IRQ21 21 +#define SCIS_IRQ22 22 +#define SCIS_IRQ23 23 + +/* P-state configuration */ +#define PSS_MAX_ENTRIES 8 +#define PSS_RATIO_STEP 2 +#define PSS_LATENCY_TRANSITION 10 +#define PSS_LATENCY_BUSMASTER 10 + +#ifndef __ASSEMBLY__ +/* Track power state from reset to log events. */ +struct __packed chipset_power_state { + u16 pm1_sts; + u16 pm1_en; + u32 pm1_cnt; + u32 gpe0_sts[GPE0_REG_MAX]; + u32 gpe0_en[GPE0_REG_MAX]; + u16 tco1_sts; + u16 tco2_sts; + u32 prsts; + u32 gen_pmcon1; + u32 gen_pmcon2; + u32 gen_pmcon3; + u32 prev_sleep_state; +}; +#endif /* !__ASSEMBLY__ */ #endif diff --git a/include/power/acpi_pmc.h b/include/power/acpi_pmc.h index 5fbf745136..222288b71a 100644 --- a/include/power/acpi_pmc.h +++ b/include/power/acpi_pmc.h @@ -6,7 +6,7 @@ #ifndef __ACPI_PMC_H #define __ACPI_PMC_H -#ifndef __ACPI__ +#ifndef __ASSEMBLY__ enum { GPE0_REG_MAX = 4, @@ -194,6 +194,6 @@ void pmc_dump_info(struct udevice *dev); */ int pmc_gpe_init(struct udevice *dev); -#endif /* !__ACPI__ */ +#endif /* !__ASSEMBLY__ */ #endif