From patchwork Mon Jan 27 05:06:05 2020
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X-Patchwork-Submitter: Simon Glass <sjg@chromium.org>
X-Patchwork-Id: 240212
List-Id: U-Boot discussion <u-boot.lists.denx.de>
From: sjg at chromium.org (Simon Glass)
Date: Sun, 26 Jan 2020 22:06:05 -0700
Subject: [PATCH 058/108] x86: apl: Support set_hide() in p2sb driver
In-Reply-To: <20200127050655.170614-1-sjg@chromium.org>
References: <20200127050655.170614-1-sjg@chromium.org>
Message-ID: <20200126220508.58.Id91837de4ede32b7f67f8cd29c7e6903a5d97f5e@changeid>

Add support for this new method in the driver and in the fsp-s setup.

Signed-off-by: Simon Glass <sjg at chromium.org>
---

 arch/x86/cpu/apollolake/fsp_s.c | 27 ++++++++++-----------------
 arch/x86/cpu/apollolake/p2sb.c  | 30 ++++++++++++++++++++++++++++++
 2 files changed, 40 insertions(+), 17 deletions(-)

diff --git a/arch/x86/cpu/apollolake/fsp_s.c b/arch/x86/cpu/apollolake/fsp_s.c
index 3ee816f44b..e7e0c30873 100644
--- a/arch/x86/cpu/apollolake/fsp_s.c
+++ b/arch/x86/cpu/apollolake/fsp_s.c
@@ -9,6 +9,7 @@
 #include <binman.h>
 #include <dm.h>
 #include <irq.h>
+#include <p2sb.h>
 #include <asm/intel_pinctrl.h>
 #include <asm/io.h>
 #include <asm/intel_regs.h>
@@ -19,9 +20,7 @@
 #include <asm/arch/systemagent.h>
 #include <asm/arch/fsp/fsp_configs.h>
 #include <asm/arch/fsp/fsp_s_upd.h>
-
-#define PCH_P2SB_E0		0xe0
-#define HIDE_BIT		BIT(0)
+#include <dm/uclass-internal.h>
 
 #define INTEL_GSPI_MAX		3
 #define MAX_USB2_PORTS		8
@@ -433,12 +432,6 @@ int fsps_update_config(struct udevice *dev, ulong rom_offset,
 	return 0;
 }
 
-static void p2sb_set_hide_bit(pci_dev_t dev, int hide)
-{
-	pci_x86_clrset_config(dev, PCH_P2SB_E0 + 1, HIDE_BIT,
-			      hide ? HIDE_BIT : 0, PCI_SIZE_8);
-}
-
 /* Configure package power limits */
 static int set_power_limits(struct udevice *dev)
 {
@@ -511,15 +504,15 @@ static int set_power_limits(struct udevice *dev)
 
 int p2sb_unhide(void)
 {
-	pci_dev_t dev = PCI_BDF(0, 0xd, 0);
-	ulong val;
-
-	p2sb_set_hide_bit(dev, 0);
-
-	pci_x86_read_config(dev, PCI_VENDOR_ID, &val, PCI_SIZE_16);
+	struct udevice *dev;
+	int ret;
 
-	if (val != PCI_VENDOR_ID_INTEL)
-		return log_msg_ret("p2sb unhide", -EIO);
+	ret = uclass_find_first_device(UCLASS_P2SB, &dev);
+	if (ret)
+		return log_msg_ret("p2sb", ret);
+	ret = p2sb_set_hide(dev, false);
+	if (ret)
+		return log_msg_ret("hide", ret);
 
 	return 0;
 }
diff --git a/arch/x86/cpu/apollolake/p2sb.c b/arch/x86/cpu/apollolake/p2sb.c
index a3d8e094e7..92bf31333c 100644
--- a/arch/x86/cpu/apollolake/p2sb.c
+++ b/arch/x86/cpu/apollolake/p2sb.c
@@ -14,6 +14,9 @@
 #include <spl.h>
 #include <asm/pci.h>
 
+#define PCH_P2SB_E0		0xe0
+#define HIDE_BIT		BIT(0)
+
 struct p2sb_platdata {
 #if CONFIG_IS_ENABLED(OF_PLATDATA)
 	struct dtd_intel_apl_p2sb dtplat;
@@ -125,6 +128,29 @@ static int apl_p2sb_probe(struct udevice *dev)
 	return 0;
 }
 
+static void p2sb_set_hide_bit(struct udevice *dev, bool hide)
+{
+	dm_pci_clrset_config8(dev, PCH_P2SB_E0 + 1, HIDE_BIT,
+			      hide ? HIDE_BIT : 0);
+}
+
+static int apl_p2sb_set_hide(struct udevice *dev, bool hide)
+{
+	u16 vendor;
+
+	if (!CONFIG_IS_ENABLED(PCI))
+		return -EPERM;
+	p2sb_set_hide_bit(dev, hide);
+
+	dm_pci_read_config16(dev, PCI_VENDOR_ID, &vendor);
+	if (hide && vendor != 0xffff)
+		return log_msg_ret("hide", -EEXIST);
+	else if (!hide && vendor != PCI_VENDOR_ID_INTEL)
+		return log_msg_ret("unhide", -ENOMEDIUM);
+
+	return 0;
+}
+
 static int p2sb_child_post_bind(struct udevice *dev)
 {
 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
@@ -141,6 +167,10 @@ static int p2sb_child_post_bind(struct udevice *dev)
 	return 0;
 }
 
+struct p2sb_ops apl_p2sb_ops = {
+	.set_hide	= apl_p2sb_set_hide,
+};
+
 static const struct udevice_id apl_p2sb_ids[] = {
 	{ .compatible = "intel,apl-p2sb" },
 	{ }