From patchwork Tue Jan 21 19:03:10 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 239898 List-Id: U-Boot discussion From: marex at denx.de (Marek Vasut) Date: Tue, 21 Jan 2020 20:03:10 +0100 Subject: [PATCH V2 2/3] mtd: rawnand: denali_dt: make the core clock optional In-Reply-To: <20200121190311.3699-1-marex@denx.de> References: <20200121190311.3699-1-marex@denx.de> Message-ID: <20200121190311.3699-2-marex@denx.de> From: Masahiro Yamada The "nand_x" and "ecc" clocks are currently optional. Make the core clock optional in the same way. This will allow platforms with no clock driver support to use this driver. Signed-off-by: Masahiro Yamada Tested-by: Marek Vasut # On SoCFPGA Arria V --- V2: No change --- drivers/mtd/nand/raw/denali_dt.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/mtd/nand/raw/denali_dt.c b/drivers/mtd/nand/raw/denali_dt.c index 0ce81324b9..b1e14982c4 100644 --- a/drivers/mtd/nand/raw/denali_dt.c +++ b/drivers/mtd/nand/raw/denali_dt.c @@ -91,7 +91,7 @@ static int denali_dt_probe(struct udevice *dev) if (ret) ret = clk_get_by_index(dev, 0, &clk); if (ret) - return ret; + clk.dev = NULL; ret = clk_get_by_name(dev, "nand_x", &clk_x); if (ret) @@ -101,9 +101,11 @@ static int denali_dt_probe(struct udevice *dev) if (ret) clk_ecc.dev = NULL; - ret = clk_enable(&clk); - if (ret) - return ret; + if (clk.dev) { + ret = clk_enable(&clk); + if (ret) + return ret; + } if (clk_x.dev) { ret = clk_enable(&clk_x);