| Message ID | 20200121190311.3699-1-marex@denx.de |
|---|---|
| State | Accepted |
| Commit | 33672c970b0854586b3c533f3bf17056e96d7cf6 |
| Headers | show |
| Series | [V2,1/3] mtd: rawnand: denali-spl: Add missing hardware init on SoCFPGA | expand |
Hi. On Wed, Jan 22, 2020 at 4:03 AM Marek Vasut <marex at denx.de> wrote: > > On Altera SoCFPGA, upon either cold-boot or power-on reset, the > Denali NAND IP is initialized by the BootROM ; upon warm-reset, > the Denali NAND IP is NOT initialized by BootROM. In fact, upon > warm-reset, the SoCFPGA BootROM checks whether the SPL image in > on-chip RAM is valid and if so, completely skips re-loading the > SPL from the boot media. > > This does sometimes leads to problems where the software left > the boot media in inconsistent state before warm-reset, and > because the BootROM does not reset the boot media, the boot > media is left in this inconsistent state, often until another > component attempts to access the boot media and fails with an > difficult to debug failure. To mitigate this problem, the SPL > on Altera SoCFPGA always resets all the IPs on the SoC early > on boot. > > This results in a couple of register values, pre-programmed by > the BootROM, to be lost during this reset. To restore correct > operation of the IP on SoCFPGA, these values must be programmed > back into the controller by the driver. Note that on other SoCs > which do not use the HW-controlled bootstrap, more registers > may have to be programmed. > > This also aligns the SPL behavior with the full Denali NAND > driver, which sets these values in denali_hw_init(). > > Signed-off-by: Marek Vasut <marex at denx.de> > Cc: Masahiro Yamada <yamada.masahiro at socionext.com> > --- Thanks for the update. I will queue this series up, and send one more fix (add udelay after the reset deassert). Thank you. > V2: Reword the commit message > --- > drivers/mtd/nand/raw/denali_spl.c | 7 +++++++ > 1 file changed, 7 insertions(+) > > diff --git a/drivers/mtd/nand/raw/denali_spl.c b/drivers/mtd/nand/raw/denali_spl.c > index dbaba3cab2..b8b29812aa 100644 > --- a/drivers/mtd/nand/raw/denali_spl.c > +++ b/drivers/mtd/nand/raw/denali_spl.c > @@ -173,6 +173,13 @@ void nand_init(void) > page_size = readl(denali_flash_reg + DEVICE_MAIN_AREA_SIZE); > oob_size = readl(denali_flash_reg + DEVICE_SPARE_AREA_SIZE); > pages_per_block = readl(denali_flash_reg + PAGES_PER_BLOCK); > + > + /* Do as denali_hw_init() does. */ > + writel(CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES, > + denali_flash_reg + SPARE_AREA_SKIP_BYTES); > + writel(0x0F, denali_flash_reg + RB_PIN_ENABLED); > + writel(CHIP_EN_DONT_CARE__FLAG, denali_flash_reg + CHIP_ENABLE_DONT_CARE); > + writel(0xffff, denali_flash_reg + SPARE_AREA_MARKER); > } > > int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst) > -- > 2.24.1 >
On Wed, Jan 22, 2020 at 4:03 AM Marek Vasut <marex at denx.de> wrote: > > On Altera SoCFPGA, upon either cold-boot or power-on reset, the > Denali NAND IP is initialized by the BootROM ; upon warm-reset, > the Denali NAND IP is NOT initialized by BootROM. In fact, upon > warm-reset, the SoCFPGA BootROM checks whether the SPL image in > on-chip RAM is valid and if so, completely skips re-loading the > SPL from the boot media. > > This does sometimes leads to problems where the software left > the boot media in inconsistent state before warm-reset, and > because the BootROM does not reset the boot media, the boot > media is left in this inconsistent state, often until another > component attempts to access the boot media and fails with an > difficult to debug failure. To mitigate this problem, the SPL > on Altera SoCFPGA always resets all the IPs on the SoC early > on boot. > > This results in a couple of register values, pre-programmed by > the BootROM, to be lost during this reset. To restore correct > operation of the IP on SoCFPGA, these values must be programmed > back into the controller by the driver. Note that on other SoCs > which do not use the HW-controlled bootstrap, more registers > may have to be programmed. > > This also aligns the SPL behavior with the full Denali NAND > driver, which sets these values in denali_hw_init(). > > Signed-off-by: Marek Vasut <marex at denx.de> > Cc: Masahiro Yamada <yamada.masahiro at socionext.com> > --- Applied to u-boot-uniphier. Thanks. > V2: Reword the commit message > --- > drivers/mtd/nand/raw/denali_spl.c | 7 +++++++ > 1 file changed, 7 insertions(+) > > diff --git a/drivers/mtd/nand/raw/denali_spl.c b/drivers/mtd/nand/raw/denali_spl.c > index dbaba3cab2..b8b29812aa 100644 > --- a/drivers/mtd/nand/raw/denali_spl.c > +++ b/drivers/mtd/nand/raw/denali_spl.c > @@ -173,6 +173,13 @@ void nand_init(void) > page_size = readl(denali_flash_reg + DEVICE_MAIN_AREA_SIZE); > oob_size = readl(denali_flash_reg + DEVICE_SPARE_AREA_SIZE); > pages_per_block = readl(denali_flash_reg + PAGES_PER_BLOCK); > + > + /* Do as denali_hw_init() does. */ > + writel(CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES, > + denali_flash_reg + SPARE_AREA_SKIP_BYTES); > + writel(0x0F, denali_flash_reg + RB_PIN_ENABLED); > + writel(CHIP_EN_DONT_CARE__FLAG, denali_flash_reg + CHIP_ENABLE_DONT_CARE); > + writel(0xffff, denali_flash_reg + SPARE_AREA_MARKER); > } > > int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst) > -- > 2.24.1 >
diff --git a/drivers/mtd/nand/raw/denali_spl.c b/drivers/mtd/nand/raw/denali_spl.c index dbaba3cab2..b8b29812aa 100644 --- a/drivers/mtd/nand/raw/denali_spl.c +++ b/drivers/mtd/nand/raw/denali_spl.c @@ -173,6 +173,13 @@ void nand_init(void) page_size = readl(denali_flash_reg + DEVICE_MAIN_AREA_SIZE); oob_size = readl(denali_flash_reg + DEVICE_SPARE_AREA_SIZE); pages_per_block = readl(denali_flash_reg + PAGES_PER_BLOCK); + + /* Do as denali_hw_init() does. */ + writel(CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES, + denali_flash_reg + SPARE_AREA_SKIP_BYTES); + writel(0x0F, denali_flash_reg + RB_PIN_ENABLED); + writel(CHIP_EN_DONT_CARE__FLAG, denali_flash_reg + CHIP_ENABLE_DONT_CARE); + writel(0xffff, denali_flash_reg + SPARE_AREA_MARKER); } int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst)
On Altera SoCFPGA, upon either cold-boot or power-on reset, the Denali NAND IP is initialized by the BootROM ; upon warm-reset, the Denali NAND IP is NOT initialized by BootROM. In fact, upon warm-reset, the SoCFPGA BootROM checks whether the SPL image in on-chip RAM is valid and if so, completely skips re-loading the SPL from the boot media. This does sometimes leads to problems where the software left the boot media in inconsistent state before warm-reset, and because the BootROM does not reset the boot media, the boot media is left in this inconsistent state, often until another component attempts to access the boot media and fails with an difficult to debug failure. To mitigate this problem, the SPL on Altera SoCFPGA always resets all the IPs on the SoC early on boot. This results in a couple of register values, pre-programmed by the BootROM, to be lost during this reset. To restore correct operation of the IP on SoCFPGA, these values must be programmed back into the controller by the driver. Note that on other SoCs which do not use the HW-controlled bootstrap, more registers may have to be programmed. This also aligns the SPL behavior with the full Denali NAND driver, which sets these values in denali_hw_init(). Signed-off-by: Marek Vasut <marex at denx.de> Cc: Masahiro Yamada <yamada.masahiro at socionext.com> --- V2: Reword the commit message --- drivers/mtd/nand/raw/denali_spl.c | 7 +++++++ 1 file changed, 7 insertions(+)