From patchwork Fri Jan 17 11:02:01 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Giulio Benetti X-Patchwork-Id: 239720 List-Id: U-Boot discussion From: giulio.benetti at benettiengineering.com (Giulio Benetti) Date: Fri, 17 Jan 2020 12:02:01 +0100 Subject: [PATCH 3/3] clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() In-Reply-To: <20200117110201.15959-1-giulio.benetti@benettiengineering.com> References: <20200117110201.15959-1-giulio.benetti@benettiengineering.com> Message-ID: <20200117110201.15959-4-giulio.benetti@benettiengineering.com> Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). Also, guard 'parent_rate<0' that would mean that clk_get_parent_rate() returned an error, so better to return early with error EINVAL. Signed-off-by: Giulio Benetti --- drivers/clk/imx/clk-pllv3.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/clk/imx/clk-pllv3.c b/drivers/clk/imx/clk-pllv3.c index d2bb1e86e1..5383ef4816 100644 --- a/drivers/clk/imx/clk-pllv3.c +++ b/drivers/clk/imx/clk-pllv3.c @@ -176,13 +176,19 @@ static ulong clk_pllv3_av_set_rate(struct clk *clk, ulong rate) { struct clk_pllv3 *pll = to_clk_pllv3(clk); unsigned long parent_rate = clk_get_parent_rate(clk); - unsigned long min_rate = parent_rate * 27; - unsigned long max_rate = parent_rate * 54; + unsigned long min_rate; + unsigned long max_rate; u32 val, div; u32 mfn, mfd = 1000000; u32 max_mfd = 0x3FFFFFFF; u64 temp64; + if (parent_rate <= 0) + return -EINVAL; + + min_rate = parent_rate * 27; + max_rate = parent_rate * 54; + if (rate < min_rate || rate > max_rate) return -EINVAL;