From patchwork Sat Jan 11 19:36:35 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joel Johnson X-Patchwork-Id: 239473 List-Id: U-Boot discussion From: mrjoel at lixil.net (Joel Johnson) Date: Sat, 11 Jan 2020 12:36:35 -0700 Subject: [PATCH 06/10] arm: mvebu: clearfog: Add config for 2GB SOM In-Reply-To: <20200111193639.19022-1-mrjoel@lixil.net> References: <20200111193639.19022-1-mrjoel@lixil.net> Message-ID: <20200111193639.19022-6-mrjoel@lixil.net> While 1GB SOM parts are much more common, provide a build config option for supporting parts with 2GB. Signed-off-by: Joel Johnson --- board/solidrun/clearfog/Kconfig | 6 ++++++ board/solidrun/clearfog/clearfog.c | 8 ++++++++ 2 files changed, 14 insertions(+) diff --git a/board/solidrun/clearfog/Kconfig b/board/solidrun/clearfog/Kconfig index 53f01daf7a..fd880ee591 100644 --- a/board/solidrun/clearfog/Kconfig +++ b/board/solidrun/clearfog/Kconfig @@ -31,4 +31,10 @@ config CLEARFOG_SFP_25GB SGMII connection (requires a supporting SFP). By default, transfer speed of 1.25 Gbps is used, suitable for a more common 1 Gbps SFP module. +config CLEARFOG_2GB_SOM + bool "Configure for a SOM with 2GB RAM" + help + Enable support for the 2GB RAM SOM variant. If this option is not + enabled then the more common 1GB version will be used. + endmenu diff --git a/board/solidrun/clearfog/clearfog.c b/board/solidrun/clearfog/clearfog.c index 247785ac56..38f411b942 100644 --- a/board/solidrun/clearfog/clearfog.c +++ b/board/solidrun/clearfog/clearfog.c @@ -67,11 +67,19 @@ static struct mv_ddr_topology_map board_topology_map = { DEBUG_LEVEL_ERROR, 0x1, /* active interfaces */ /* cs_mask, mirror, dqs_swap, ck_swap X PUPs */ +#if defined (CONFIG_CLEARFOG_2GB_SOM) + { { { {0x3, 0, 0, 0}, + {0x3, 0, 0, 0}, + {0x3, 0, 0, 0}, + {0x3, 0, 0, 0}, + {0x3, 0, 0, 0} }, +#else { { { {0x1, 0, 0, 0}, {0x1, 0, 0, 0}, {0x1, 0, 0, 0}, {0x1, 0, 0, 0}, {0x1, 0, 0, 0} }, +#endif SPEED_BIN_DDR_1600K, /* speed_bin */ MV_DDR_DEV_WIDTH_16BIT, /* memory_width */ MV_DDR_DIE_CAP_4GBIT, /* mem_size */