@@ -242,6 +242,7 @@ config FSL_LSCH2
select SYS_FSL_SEC_BE
config FSL_LSCH3
+ select ARCH_MISC_INIT
bool
config NXP_LSCH3_2
@@ -1630,3 +1630,17 @@ __weak int dram_init(void)
return 0;
}
+
+#ifdef CONFIG_ARCH_MISC_INIT
+__weak int serdes_misc_init(void)
+{
+ return 0;
+}
+
+int arch_misc_init(void)
+{
+ serdes_misc_init();
+
+ return 0;
+}
+#endif
@@ -600,3 +600,62 @@ void fsl_serdes_init(void)
serdes3_prtcl_map);
#endif
}
+
+int serdes_set_env(int sd, int rcwsr, int sd_prctl_mask, int sd_prctl_shift)
+{
+ struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ char scfg[16], snum[16];
+ int cfgr = 0;
+ u32 cfg;
+
+ cfg = gur_in32(&gur->rcwsr[rcwsr - 1]) & sd_prctl_mask;
+ cfg >>= sd_prctl_shift;
+ cfg = serdes_get_number(sd, cfg);
+
+#if defined(SRDS_BITS_PER_LANE)
+ /*
+ * reverse lanes, lane 0 should be printed first so it must be moved to
+ * high order bits.
+ * For example bb58 should read 85bb, lane 0 being protocol 8.
+ * This only applies to SoCs that define SRDS_BITS_PER_LANE and have
+ * independent per-lane protocol configuration, at this time LS1028A and
+ * LS1088A. LS2 and LX2 SoCs encode the full protocol mix across all
+ * lanes as a single value.
+ */
+ for (int i = 0; i < SRDS_MAX_LANES; i++) {
+ int tmp;
+
+ tmp = cfg >> (i * SRDS_BITS_PER_LANE);
+ tmp &= GENMASK(SRDS_BITS_PER_LANE - 1, 0);
+ tmp <<= (SRDS_MAX_LANES - i - 1) * SRDS_BITS_PER_LANE;
+ cfgr |= tmp;
+ }
+#endif /* SRDS_BITS_PER_LANE */
+
+ snprintf(snum, 16, "serdes%d", sd);
+ snprintf(scfg, 16, "%x", cfgr);
+ env_set(snum, scfg);
+
+ return 0;
+}
+
+int serdes_misc_init(void)
+{
+#ifdef CONFIG_SYS_FSL_SRDS_1
+ serdes_set_env(FSL_SRDS_1, FSL_CHASSIS3_SRDS1_REGSR,
+ FSL_CHASSIS3_SRDS1_PRTCL_MASK,
+ FSL_CHASSIS3_SRDS1_PRTCL_SHIFT);
+#endif
+#ifdef CONFIG_SYS_FSL_SRDS_2
+ serdes_set_env(FSL_SRDS_2, FSL_CHASSIS3_SRDS2_REGSR,
+ FSL_CHASSIS3_SRDS2_PRTCL_MASK,
+ FSL_CHASSIS3_SRDS2_PRTCL_SHIFT);
+#endif
+#ifdef CONFIG_SYS_NXP_SRDS_3
+ serdes_set_env(NXP_SRDS_3, FSL_CHASSIS3_SRDS3_REGSR,
+ FSL_CHASSIS3_SRDS3_PRTCL_MASK,
+ FSL_CHASSIS3_SRDS3_PRTCL_SHIFT);
+#endif
+
+ return 0;
+}
@@ -123,6 +123,7 @@
#define CONFIG_SYS_PAGE_SIZE 0x10000
#define SRDS_MAX_LANES 4
+#define SRDS_BITS_PER_LANE 4
/* TZ Protection Controller Definitions */
#define TZPC_BASE 0x02200000
@@ -252,6 +253,7 @@
#define TZPCDECPROT_2_CLR_BASE (TZPC_BASE + 0x820)
#define SRDS_MAX_LANES 4
+#define SRDS_BITS_PER_LANE 4
#define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */
#define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M */
Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean at nxp.com> --- arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 1 + arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 14 +++++ .../armv8/fsl-layerscape/fsl_lsch3_serdes.c | 59 +++++++++++++++++++ .../include/asm/arch-fsl-layerscape/config.h | 2 + 4 files changed, 76 insertions(+)