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[81.169.180.215]) by mx.google.com with ESMTP id h11si801910edw.123.2018.11.27.04.52.46; Tue, 27 Nov 2018 04:52:46 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=c9a5uyg1; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: by lists.denx.de (Postfix, from userid 105) id 884FCC222C0; Tue, 27 Nov 2018 12:51:46 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id CD59EC222E7; Tue, 27 Nov 2018 12:50:25 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 59E78C22220; Tue, 27 Nov 2018 12:50:19 +0000 (UTC) Received: from mail-wr1-f65.google.com (mail-wr1-f65.google.com [209.85.221.65]) by lists.denx.de (Postfix) with ESMTPS id 7A30CC222E2 for ; Tue, 27 Nov 2018 12:50:15 +0000 (UTC) Received: by mail-wr1-f65.google.com with SMTP id r10so22540759wrs.10 for ; Tue, 27 Nov 2018 04:50:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=WWMCIyh/1tnrKtJsr1WR40GPCSUe2CSAco7WXy3DfX4=; b=c9a5uyg15dZzjqXNgtMdMrblovgL1vHITa4A1iIlRHqJuCp6D7JwY6/aYA+IxPYUef pVF/JyYDtv21H1LyCghEtPWcTK6Say/oQgHvrSq5yIfaJfyxtTBBGbF0G9NNK6dVIOmA 1HBL62Z4oqRWcR12rdzTwn+9ENfPo9EI3PeZA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=WWMCIyh/1tnrKtJsr1WR40GPCSUe2CSAco7WXy3DfX4=; b=QFelNI1E7L05sSsWX7oDcYy1R8y6Vv1HjEJ0zBfvrVaRSUGv2oRFtxX3cW01HljVZe IlkZRvVfZetQTtJEpIVtUtBG8J+rc8f5w6AUw2lITKdA/zKk+CTcL6j0VpkYAv7HOaJm 2hvVkSjReW4zUWfyyIw2mrLffxK+ppnCEDU6rpAVKakuedi5R1FfyTzTfOsSk8HMIwH7 Bwp5F7tjc8/whQBzUmiHA2N4OrUWRvjUBY3lPL1Z4zKdw4n1ITMGOgxPNCFAoRIz4elK uC120CMFOaDrKNchsWWbN9yrZ4HZjsO7TYDLjyFcgo2DLlJv/VjZGdfynw0wDJN5NmQY 4HTg== X-Gm-Message-State: AA+aEWad6lHRCrbUXM9IzZ6fiY2MIpzdvq/qqGCg+cBUrFZ3avKlyrw5 uFSDx+ky7UM2yBde2/JQ1fz5QQ== X-Received: by 2002:adf:f189:: with SMTP id h9mr27308146wro.35.1543323015003; Tue, 27 Nov 2018 04:50:15 -0800 (PST) Received: from lmecxl0911.lme.st.com ([2a04:cec0:1087:3904:205d:1327:2414:27b8]) by smtp.gmail.com with ESMTPSA id p14sm3098056wrt.37.2018.11.27.04.50.13 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 27 Nov 2018 04:50:14 -0800 (PST) From: Benjamin Gaignard X-Google-Original-From: Benjamin Gaignard To: patrick.delaunay@st.com, albert.u.boot@aribaud.net, sjg@chromium.org, christophe.kerello@st.com, patrice.chotard@st.com, trini@konsulko.com Date: Tue, 27 Nov 2018 13:49:53 +0100 Message-Id: <20181127124953.4458-5-benjamin.gaignard@st.com> X-Mailer: git-send-email 2.15.0 In-Reply-To: <20181127124953.4458-1-benjamin.gaignard@st.com> References: <20181127124953.4458-1-benjamin.gaignard@st.com> MIME-Version: 1.0 Cc: uboot-stm32@st-md-mailman.stormreply.com, u-boot@lists.denx.de, Benjamin Gaignard Subject: [U-Boot] [PATCH v5 4/4] pinctrl: stm32: make pinctrl use hwspinlock X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Protect configuration registers with a hardware spinlock. If a hwspinlock is defined in the device-tree node used it to be sure that none of the others processors on the SoC could change the configuration at the same time. Signed-off-by: Benjamin Gaignard Reviewed-by: Simon Glass Reviewed-by: Patrice Chotard --- version 5: ²- rebased on top of master branch arch/arm/dts/stm32mp157c-ed1.dts | 4 ++++ drivers/pinctrl/pinctrl_stm32.c | 27 +++++++++++++++++++++++---- 2 files changed, 27 insertions(+), 4 deletions(-) diff --git a/arch/arm/dts/stm32mp157c-ed1.dts b/arch/arm/dts/stm32mp157c-ed1.dts index fc277dd7d2..7a9b742d36 100644 --- a/arch/arm/dts/stm32mp157c-ed1.dts +++ b/arch/arm/dts/stm32mp157c-ed1.dts @@ -369,6 +369,10 @@ status = "okay"; }; +&pinctrl { + hwlocks = <&hwspinlock 0>; +}; + &usbphyc_port0 { phy-supply = <&vdd_usb>; vdda1v1-supply = <®11>; diff --git a/drivers/pinctrl/pinctrl_stm32.c b/drivers/pinctrl/pinctrl_stm32.c index 6d4117d941..bb63da3739 100644 --- a/drivers/pinctrl/pinctrl_stm32.c +++ b/drivers/pinctrl/pinctrl_stm32.c @@ -1,6 +1,7 @@ #include #include #include +#include #include #include #include @@ -14,8 +15,8 @@ DECLARE_GLOBAL_DATA_PTR; #define OTYPE_MSK 1 #define AFR_MASK 0xF -#ifndef CONFIG_SPL_BUILD struct stm32_pinctrl_priv { + struct hwspinlock hws; int pinctrl_ngpios; struct list_head gpio_dev; }; @@ -25,6 +26,8 @@ struct stm32_gpio_bank { struct list_head list; }; +#ifndef CONFIG_SPL_BUILD + #define MAX_PIN_PER_BANK 16 static char pin_name[PINNAME_SIZE]; @@ -166,6 +169,8 @@ static int stm32_pinctrl_get_pin_muxing(struct udevice *dev, return 0; } +#endif + int stm32_pinctrl_probe(struct udevice *dev) { struct stm32_pinctrl_priv *priv = dev_get_priv(dev); @@ -198,21 +203,35 @@ int stm32_pinctrl_probe(struct udevice *dev) list_add_tail(&gpio_bank->list, &priv->gpio_dev); } + /* hwspinlock property is optional, just log the error */ + ret = hwspinlock_get_by_index(dev, 0, &priv->hws); + if (ret) + debug("%s: hwspinlock_get_by_index may have failed (%d)\n", + __func__, ret); + return 0; } -#endif static int stm32_gpio_config(struct gpio_desc *desc, const struct stm32_gpio_ctl *ctl) { struct stm32_gpio_priv *priv = dev_get_priv(desc->dev); struct stm32_gpio_regs *regs = priv->regs; + struct stm32_pinctrl_priv *ctrl_priv; + int ret; u32 index; if (!ctl || ctl->af > 15 || ctl->mode > 3 || ctl->otype > 1 || ctl->pupd > 2 || ctl->speed > 3) return -EINVAL; + ctrl_priv = dev_get_priv(dev_get_parent(desc->dev)); + ret = hwspinlock_lock_timeout(&ctrl_priv->hws, 10); + if (ret == -ETIME) { + dev_err(desc->dev, "HWSpinlock timeout\n"); + return ret; + } + index = (desc->offset & 0x07) * 4; clrsetbits_le32(®s->afr[desc->offset >> 3], AFR_MASK << index, ctl->af << index); @@ -227,6 +246,8 @@ static int stm32_gpio_config(struct gpio_desc *desc, index = desc->offset; clrsetbits_le32(®s->otyper, OTYPE_MSK << index, ctl->otype << index); + hwspinlock_unlock(&ctrl_priv->hws); + return 0; } @@ -393,8 +414,6 @@ U_BOOT_DRIVER(pinctrl_stm32) = { .of_match = stm32_pinctrl_ids, .ops = &stm32_pinctrl_ops, .bind = dm_scan_fdt_dev, -#ifndef CONFIG_SPL_BUILD .probe = stm32_pinctrl_probe, .priv_auto_alloc_size = sizeof(struct stm32_pinctrl_priv), -#endif };