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[81.169.180.215]) by mx.google.com with ESMTP id g5-v6si1933000ejp.46.2018.11.27.04.52.31; Tue, 27 Nov 2018 04:52:32 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=YBJtrHZF; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: by lists.denx.de (Postfix, from userid 105) id D1283C22220; Tue, 27 Nov 2018 12:51:08 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id E3F9AC222EA; Tue, 27 Nov 2018 12:50:20 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id EF7B2C22283; Tue, 27 Nov 2018 12:50:15 +0000 (UTC) Received: from mail-wm1-f66.google.com (mail-wm1-f66.google.com [209.85.128.66]) by lists.denx.de (Postfix) with ESMTPS id 8B7E4C220EC for ; Tue, 27 Nov 2018 12:50:11 +0000 (UTC) Received: by mail-wm1-f66.google.com with SMTP id n133so5297067wmd.4 for ; Tue, 27 Nov 2018 04:50:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=oLp9ZZs9aCvjbUr7WBcd79aLnWxjPpZLbs2+aMbjkOE=; b=YBJtrHZFpCVlMh3Lmf0IIbCOeUZv9wPhVAgVcFdoSmYU9o1UwCik/Dr48Vkz2Xn4h1 t58FTawzJDfNi2UPUW2A7JiA/EB1L/OVZ7z5rg9G51NyOUUhk3hsnoTnsz1UuO3ss3T/ qXzAbW0O4874orUfnhxcevA2aJzkVahIwhco0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=oLp9ZZs9aCvjbUr7WBcd79aLnWxjPpZLbs2+aMbjkOE=; b=OwdGEalOX/M+VWAux5ZF5ahYpPbbPZcd2xkJRHBFrlu3MH2sT7YteEk4vKljGTxIel 8Z7fhg+tGJ3ayyS1lGn797WpwIvF5ZLZ6vynUKFuRa4t1gQhsQmSO8sKvCzp3IViU+// TxPnofOQPaB3xar5q9vt8ry0MWsWr75chRPZ3Uvj4GzjDXqhVjo/i+TLdEYNYj3sUIrJ R1cseQna8I1u+EBI+/YcgXsHADPZgKH4hjCqOWZIPL234bjYeLzJjQmCNvne6RB4RPFJ Ze3PTbgj6hpc5a7ZuX7aYoFU9fFrgCiGpTpgaCHuegY+yfVe353Wp5gaol4d2/CrtL7s bhrw== X-Gm-Message-State: AA+aEWZnYw6xoHqJv5yVHQSwBF5qHnohS20/ar+dUjQNmAh0/Se6bXba mxYvoP1Axfa/j5vQFgh8pCs7Z1HXZ0U= X-Received: by 2002:a1c:b687:: with SMTP id g129mr9506855wmf.59.1543323011216; Tue, 27 Nov 2018 04:50:11 -0800 (PST) Received: from lmecxl0911.lme.st.com ([2a04:cec0:1087:3904:205d:1327:2414:27b8]) by smtp.gmail.com with ESMTPSA id p14sm3098056wrt.37.2018.11.27.04.50.09 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 27 Nov 2018 04:50:10 -0800 (PST) From: Benjamin Gaignard X-Google-Original-From: Benjamin Gaignard To: patrick.delaunay@st.com, albert.u.boot@aribaud.net, sjg@chromium.org, christophe.kerello@st.com, patrice.chotard@st.com, trini@konsulko.com Date: Tue, 27 Nov 2018 13:49:51 +0100 Message-Id: <20181127124953.4458-3-benjamin.gaignard@st.com> X-Mailer: git-send-email 2.15.0 In-Reply-To: <20181127124953.4458-1-benjamin.gaignard@st.com> References: <20181127124953.4458-1-benjamin.gaignard@st.com> Cc: uboot-stm32@st-md-mailman.stormreply.com, u-boot@lists.denx.de Subject: [U-Boot] [PATCH v5 2/4] clk: stm32: add hardware spinlock clock X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Benjamin Gaignard Add hardware spinlock in the list of the clocks. Signed-off-by: Benjamin Gaignard Reviewed-by: Simon Glass Reviewed-by: Patrice Chotard --- drivers/clk/clk_stm32mp1.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/clk/clk_stm32mp1.c b/drivers/clk/clk_stm32mp1.c index 6a8c7b754f..b7c5d34fe0 100644 --- a/drivers/clk/clk_stm32mp1.c +++ b/drivers/clk/clk_stm32mp1.c @@ -104,6 +104,7 @@ #define RCC_MP_APB2ENSETR 0XA08 #define RCC_MP_APB3ENSETR 0xA10 #define RCC_MP_AHB2ENSETR 0xA18 +#define RCC_MP_AHB3ENSETR 0xA20 #define RCC_MP_AHB4ENSETR 0xA28 /* used for most of SELR register */ @@ -534,6 +535,8 @@ static const struct stm32mp1_clk_gate stm32mp1_clk_gate[] = { STM32MP1_CLK_SET_CLR(RCC_MP_AHB2ENSETR, 8, USBO_K, _USBO_SEL), STM32MP1_CLK_SET_CLR(RCC_MP_AHB2ENSETR, 16, SDMMC3_K, _SDMMC3_SEL), + STM32MP1_CLK_SET_CLR(RCC_MP_AHB3ENSETR, 11, HSEM, _UNKNOWN_SEL), + STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 0, GPIOA, _UNKNOWN_SEL), STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 1, GPIOB, _UNKNOWN_SEL), STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 2, GPIOC, _UNKNOWN_SEL),