diff mbox series

[v5,2/4] clk: stm32: add hardware spinlock clock

Message ID 20181127124953.4458-3-benjamin.gaignard@st.com
State Accepted
Commit 283bcd9a341dcc344113daad82d8e5ab978ed260
Headers show
Series Add Hardware Spinlock class | expand

Commit Message

Benjamin Gaignard Nov. 27, 2018, 12:49 p.m. UTC 
From: Benjamin Gaignard <benjamin.gaignard@linaro.org>

Add hardware spinlock in the list of the clocks.

Signed-off-by: Benjamin Gaignard <benjamin.gaignard@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
---
 drivers/clk/clk_stm32mp1.c | 3 +++
 1 file changed, 3 insertions(+)

Comments

Tom Rini Dec. 7, 2018, 8:33 p.m. UTC | #1 
On Tue, Nov 27, 2018 at 01:49:51PM +0100, Benjamin Gaignard wrote:

> From: Benjamin Gaignard <benjamin.gaignard@linaro.org>

> 

> Add hardware spinlock in the list of the clocks.

> 

> Signed-off-by: Benjamin Gaignard <benjamin.gaignard@linaro.org>

> Reviewed-by: Simon Glass <sjg@chromium.org>

> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>


Applied to u-boot/master, thanks!

-- 
Tom
diff mbox series

Patch

diff --git a/drivers/clk/clk_stm32mp1.c b/drivers/clk/clk_stm32mp1.c
index 6a8c7b754f..b7c5d34fe0 100644
--- a/drivers/clk/clk_stm32mp1.c
+++ b/drivers/clk/clk_stm32mp1.c
@@ -104,6 +104,7 @@ 
 #define RCC_MP_APB2ENSETR	0XA08
 #define RCC_MP_APB3ENSETR	0xA10
 #define RCC_MP_AHB2ENSETR	0xA18
+#define RCC_MP_AHB3ENSETR	0xA20
 #define RCC_MP_AHB4ENSETR	0xA28
 
 /* used for most of SELR register */
@@ -534,6 +535,8 @@  static const struct stm32mp1_clk_gate stm32mp1_clk_gate[] = {
 	STM32MP1_CLK_SET_CLR(RCC_MP_AHB2ENSETR, 8, USBO_K, _USBO_SEL),
 	STM32MP1_CLK_SET_CLR(RCC_MP_AHB2ENSETR, 16, SDMMC3_K, _SDMMC3_SEL),
 
+	STM32MP1_CLK_SET_CLR(RCC_MP_AHB3ENSETR, 11, HSEM, _UNKNOWN_SEL),
+
 	STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 0, GPIOA, _UNKNOWN_SEL),
 	STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 1, GPIOB, _UNKNOWN_SEL),
 	STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 2, GPIOC, _UNKNOWN_SEL),