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[81.169.180.215]) by mx.google.com with ESMTP id i19si3938194edr.271.2018.11.16.06.03.23; Fri, 16 Nov 2018 06:03:24 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b="eg/6vBc/"; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: by lists.denx.de (Postfix, from userid 105) id 873BBC224EC; Fri, 16 Nov 2018 14:03:13 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 3493FC224E8; Fri, 16 Nov 2018 14:01:51 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id C3A16C22500; Fri, 16 Nov 2018 14:01:28 +0000 (UTC) Received: from mail-wm1-f65.google.com (mail-wm1-f65.google.com [209.85.128.65]) by lists.denx.de (Postfix) with ESMTPS id A1E2CC224E8 for ; Fri, 16 Nov 2018 14:00:57 +0000 (UTC) Received: by mail-wm1-f65.google.com with SMTP id r63-v6so22293311wma.4 for ; Fri, 16 Nov 2018 06:00:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=oLp9ZZs9aCvjbUr7WBcd79aLnWxjPpZLbs2+aMbjkOE=; b=eg/6vBc/2MGLx8eObUYpSm/WZ7ImSJOVKujNWFPwRoPJzG7qiR3m9rclXLN6WeaX/i TlTKUcEneiOO/aNtmVmfpa5rLyIZ2yF7fwaxy3DP++ori3DjAUpb8aHRdqKgoxR3Bzs0 iNU8WcNrWV8lEvq4kHmkt3Nu7UF9Ir/7cPG7c= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=oLp9ZZs9aCvjbUr7WBcd79aLnWxjPpZLbs2+aMbjkOE=; b=ASp1grrz9jMa3PjBLRNx1nUVBUp+L4eBf+s4XDHCqUnR17fX80rekohLa9JWW1Kuya qycqoNrz5t/yBdFl8h/Dtz8JzNDU8wULRFQR37gq7Euqnr5FT0nbKlCcCs70Kt2dwMFc veC+bTrfjQGgjjtS3wI5fmS4JwR2Cy/5DNhlnVzlTvVex5SNeKG+82mDcZgDI9h/6dBm 4/yyGtVt9ceSoTI1l2EZd5BnrexdWwXMyKEm6xF7TOXkOW4EkXd4zxPtATRBWgre/XJD tq2t+1zja7McwbZ+SnQLpQ38cs6X5V2syc1Uai34ZnXWVOpe/Zp7zX4AxJWI227Y29vt l1ug== X-Gm-Message-State: AGRZ1gKqoamgTDrMF8+NhZgg+vhqAjZV83Ts1VnIcPqi+SLMEo/18Z4n 8H2/KuT2LCe3pArGlQTYaj7MXA== X-Received: by 2002:a1c:248b:: with SMTP id k133-v6mr8423089wmk.148.1542376857198; Fri, 16 Nov 2018 06:00:57 -0800 (PST) Received: from lmecxl0911.lme.st.com ([2a04:cec0:105d:3df6:606e:fa38:9819:9c69]) by smtp.gmail.com with ESMTPSA id s81sm11208060wmf.14.2018.11.16.06.00.55 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 16 Nov 2018 06:00:56 -0800 (PST) From: Benjamin Gaignard X-Google-Original-From: Benjamin Gaignard To: patrick.delaunay@st.com, albert.u.boot@aribaud.net, sjg@chromium.org, christophe.kerello@st.com, patrice.chotard@st.com Date: Fri, 16 Nov 2018 15:00:37 +0100 Message-Id: <20181116140039.11628-3-benjamin.gaignard@st.com> X-Mailer: git-send-email 2.15.0 In-Reply-To: <20181116140039.11628-1-benjamin.gaignard@st.com> References: <20181116140039.11628-1-benjamin.gaignard@st.com> Cc: uboot-stm32@st-md-mailman.stormreply.com, u-boot@lists.denx.de Subject: [U-Boot] [PATCH v4 2/4] clk: stm32: add hardware spinlock clock X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Benjamin Gaignard Add hardware spinlock in the list of the clocks. Signed-off-by: Benjamin Gaignard Reviewed-by: Simon Glass Reviewed-by: Patrice Chotard --- drivers/clk/clk_stm32mp1.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/clk/clk_stm32mp1.c b/drivers/clk/clk_stm32mp1.c index 6a8c7b754f..b7c5d34fe0 100644 --- a/drivers/clk/clk_stm32mp1.c +++ b/drivers/clk/clk_stm32mp1.c @@ -104,6 +104,7 @@ #define RCC_MP_APB2ENSETR 0XA08 #define RCC_MP_APB3ENSETR 0xA10 #define RCC_MP_AHB2ENSETR 0xA18 +#define RCC_MP_AHB3ENSETR 0xA20 #define RCC_MP_AHB4ENSETR 0xA28 /* used for most of SELR register */ @@ -534,6 +535,8 @@ static const struct stm32mp1_clk_gate stm32mp1_clk_gate[] = { STM32MP1_CLK_SET_CLR(RCC_MP_AHB2ENSETR, 8, USBO_K, _USBO_SEL), STM32MP1_CLK_SET_CLR(RCC_MP_AHB2ENSETR, 16, SDMMC3_K, _SDMMC3_SEL), + STM32MP1_CLK_SET_CLR(RCC_MP_AHB3ENSETR, 11, HSEM, _UNKNOWN_SEL), + STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 0, GPIOA, _UNKNOWN_SEL), STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 1, GPIOB, _UNKNOWN_SEL), STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 2, GPIOC, _UNKNOWN_SEL),