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Tue, 13 Nov 2018 12:15:35 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id A1BA3C21ED5; Tue, 13 Nov 2018 08:52:07 +0000 (UTC) Received: from mail-wm1-f67.google.com (mail-wm1-f67.google.com [209.85.128.67]) by lists.denx.de (Postfix) with ESMTPS id 16180C21DCA for ; Tue, 13 Nov 2018 08:52:07 +0000 (UTC) Received: by mail-wm1-f67.google.com with SMTP id u13-v6so10582784wmc.4 for ; Tue, 13 Nov 2018 00:52:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=BD5rMv+N1dLdo+NQLGay9wz8+FWPDp+WsLPBmGRxhv0=; b=d3JY4j5D4ch1ZKPLNXp0sr6deIDDkoa9llx57a1x5nmNVBL8vMY8WneWhuUG8a/8Q0 ykAmq1Fe+InuuoTTvE/EvTt+C6XgmgHvMBKsmpn5hhk++5qngBNWHeyz1ELAHBhqf0Fj vOdC7L+oMnCEtMeWh7eM99HuXWL7bLihdNLto= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=BD5rMv+N1dLdo+NQLGay9wz8+FWPDp+WsLPBmGRxhv0=; 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}; +&pinctrl { + hwlocks = <&hwspinlock 0>; +}; + &usbphyc_port0 { phy-supply = <&vdd_usb>; vdda1v1-supply = <®11>; diff --git a/drivers/pinctrl/pinctrl_stm32.c b/drivers/pinctrl/pinctrl_stm32.c index 31285cdd57..469cc0c543 100644 --- a/drivers/pinctrl/pinctrl_stm32.c +++ b/drivers/pinctrl/pinctrl_stm32.c @@ -1,6 +1,7 @@ #include #include #include +#include #include #include #include @@ -19,12 +20,20 @@ static int stm32_gpio_config(struct gpio_desc *desc, { struct stm32_gpio_priv *priv = dev_get_priv(desc->dev); struct stm32_gpio_regs *regs = priv->regs; + struct hwspinlock *hws = dev_get_priv(desc->dev->parent); u32 index; + int ret; if (!ctl || ctl->af > 15 || ctl->mode > 3 || ctl->otype > 1 || ctl->pupd > 2 || ctl->speed > 3) return -EINVAL; + ret = hwspinlock_lock_timeout(hws, 1); + if (ret == -ETIME) { + dev_err(desc->dev, "HWSpinlock timeout\n"); + return ret; + } + index = (desc->offset & 0x07) * 4; clrsetbits_le32(®s->afr[desc->offset >> 3], AFR_MASK << index, ctl->af << index); @@ -39,6 +48,8 @@ static int stm32_gpio_config(struct gpio_desc *desc, index = desc->offset; clrsetbits_le32(®s->otyper, OTYPE_MSK << index, ctl->otype << index); + hwspinlock_unlock(hws); + return 0; } @@ -176,6 +187,15 @@ static int stm32_pinctrl_set_state_simple(struct udevice *dev, } #endif /* PINCTRL_FULL */ +static int stm32_pinctrl_probe(struct udevice *dev) +{ + struct hwspinlock *hws = dev_get_priv(dev); + + hwspinlock_get_by_index(dev, 0, hws); + + return 0; +} + static struct pinctrl_ops stm32_pinctrl_ops = { #if CONFIG_IS_ENABLED(PINCTRL_FULL) .set_state = stm32_pinctrl_set_state, @@ -200,4 +220,6 @@ U_BOOT_DRIVER(pinctrl_stm32) = { .of_match = stm32_pinctrl_ids, .ops = &stm32_pinctrl_ops, .bind = dm_scan_fdt_dev, + .probe = stm32_pinctrl_probe, + .priv_auto_alloc_size = sizeof(struct hwspinlock), };