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[81.169.180.215]) by mx.google.com with ESMTP id g4-v6si2468465edi.52.2018.10.25.20.42.12; Thu, 25 Oct 2018 20:42:12 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: by lists.denx.de (Postfix, from userid 105) id 832A8C21FF6; Fri, 26 Oct 2018 03:39:44 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id A5072C21E3B; Fri, 26 Oct 2018 03:38:34 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 0C5B8C21E1D; Fri, 26 Oct 2018 03:38:27 +0000 (UTC) Received: from fllv0016.ext.ti.com (fllv0016.ext.ti.com [198.47.19.142]) by lists.denx.de (Postfix) with ESMTPS id EADBAC21EB9 for ; Fri, 26 Oct 2018 03:38:26 +0000 (UTC) Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id w9Q3cLDd066427; Thu, 25 Oct 2018 22:38:21 -0500 Received: from DFLE111.ent.ti.com (dfle111.ent.ti.com [10.64.6.32]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id w9Q3cL4U087486 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 25 Oct 2018 22:38:21 -0500 Received: from DFLE102.ent.ti.com (10.64.6.23) by DFLE111.ent.ti.com (10.64.6.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1466.3; Thu, 25 Oct 2018 22:38:21 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1466.3 via Frontend Transport; Thu, 25 Oct 2018 22:38:21 -0500 Received: from legion.dal.design.ti.com (legion.dal.design.ti.com [128.247.22.53]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id w9Q3cLTg010201; Thu, 25 Oct 2018 22:38:21 -0500 Received: from localhost (uda0226610.dhcp.ti.com [128.247.59.147]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id w9Q3cLx28054; Thu, 25 Oct 2018 22:38:21 -0500 (CDT) From: Grygorii Strashko To: Vitaly Andrianov , Joe Hershberger , Lokesh Vutla , Tom Rini Date: Thu, 25 Oct 2018 22:38:16 -0500 Message-ID: <20181026033816.7544-8-grygorii.strashko@ti.com> X-Mailer: git-send-email 2.10.5 In-Reply-To: <20181026033816.7544-1-grygorii.strashko@ti.com> References: <20181026033816.7544-1-grygorii.strashko@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Cc: u-boot@lists.denx.de Subject: [U-Boot] [PATCH 7/7] driver: net: ti: keystone_net: switch to use common mdio lib X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Update TI Keystone 2 driver to re-use common mdio lib. Signed-off-by: Grygorii Strashko Reviewed-by: Tom Rini Acked-by: Joe Hershberger --- arch/arm/include/asm/ti-common/keystone_net.h | 13 --- drivers/net/ti/Makefile | 2 +- drivers/net/ti/keystone_net.c | 118 ++++---------------------- 3 files changed, 18 insertions(+), 115 deletions(-) diff --git a/arch/arm/include/asm/ti-common/keystone_net.h b/arch/arm/include/asm/ti-common/keystone_net.h index bef1867..bba1048 100644 --- a/arch/arm/include/asm/ti-common/keystone_net.h +++ b/arch/arm/include/asm/ti-common/keystone_net.h @@ -57,19 +57,6 @@ /* MDIO clock output frequency */ #define EMAC_MDIO_CLOCK_FREQ 2500000 /* 2.5 MHz */ -/* MII Status Register */ -#define MII_STATUS_REG 1 -#define MII_STATUS_LINK_MASK 0x4 - -#define MDIO_CONTROL_IDLE 0x80000000 -#define MDIO_CONTROL_ENABLE 0x40000000 -#define MDIO_CONTROL_FAULT_ENABLE 0x40000 -#define MDIO_CONTROL_FAULT 0x80000 -#define MDIO_USERACCESS0_GO 0x80000000 -#define MDIO_USERACCESS0_WRITE_READ 0x0 -#define MDIO_USERACCESS0_WRITE_WRITE 0x40000000 -#define MDIO_USERACCESS0_ACK 0x20000000 - #define EMAC_MACCONTROL_MIIEN_ENABLE 0x20 #define EMAC_MACCONTROL_FULLDUPLEX_ENABLE 0x1 #define EMAC_MACCONTROL_GIGABIT_ENABLE BIT(7) diff --git a/drivers/net/ti/Makefile b/drivers/net/ti/Makefile index d2b6f20..ee3e4eb 100644 --- a/drivers/net/ti/Makefile +++ b/drivers/net/ti/Makefile @@ -4,4 +4,4 @@ obj-$(CONFIG_DRIVER_TI_CPSW) += cpsw.o cpsw-common.o cpsw_mdio.o obj-$(CONFIG_DRIVER_TI_EMAC) += davinci_emac.o -obj-$(CONFIG_DRIVER_TI_KEYSTONE_NET) += keystone_net.o +obj-$(CONFIG_DRIVER_TI_KEYSTONE_NET) += keystone_net.o cpsw_mdio.o diff --git a/drivers/net/ti/keystone_net.c b/drivers/net/ti/keystone_net.c index 5550572..a3ba91c 100644 --- a/drivers/net/ti/keystone_net.c +++ b/drivers/net/ti/keystone_net.c @@ -22,6 +22,8 @@ #include #include +#include "cpsw_mdio.h" + DECLARE_GLOBAL_DATA_PTR; #ifdef KEYSTONE2_EMAC_GIG_ENABLE @@ -97,93 +99,20 @@ struct ks2_eth_priv { bool has_mdio; }; -/* MDIO */ - -static int keystone2_mdio_reset(struct mii_dev *bus) -{ - u_int32_t clkdiv; - struct mdio_regs *adap_mdio = bus->priv; - - clkdiv = (EMAC_MDIO_BUS_FREQ / EMAC_MDIO_CLOCK_FREQ) - 1; - - writel((clkdiv & 0xffff) | MDIO_CONTROL_ENABLE | - MDIO_CONTROL_FAULT | MDIO_CONTROL_FAULT_ENABLE, - &adap_mdio->control); - - while (readl(&adap_mdio->control) & MDIO_CONTROL_IDLE) - ; - - return 0; -} - -/** - * keystone2_mdio_read - read a PHY register via MDIO interface. - * Blocks until operation is complete. - */ -static int keystone2_mdio_read(struct mii_dev *bus, - int addr, int devad, int reg) -{ - int tmp; - struct mdio_regs *adap_mdio = bus->priv; - - while (readl(&adap_mdio->useraccess0) & MDIO_USERACCESS0_GO) - ; - - writel(MDIO_USERACCESS0_GO | MDIO_USERACCESS0_WRITE_READ | - ((reg & 0x1f) << 21) | ((addr & 0x1f) << 16), - &adap_mdio->useraccess0); - - /* Wait for command to complete */ - while ((tmp = readl(&adap_mdio->useraccess0)) & MDIO_USERACCESS0_GO) - ; - - if (tmp & MDIO_USERACCESS0_ACK) - return tmp & 0xffff; - - return -1; -} - -/** - * keystone2_mdio_write - write to a PHY register via MDIO interface. - * Blocks until operation is complete. - */ -static int keystone2_mdio_write(struct mii_dev *bus, - int addr, int devad, int reg, u16 val) -{ - struct mdio_regs *adap_mdio = bus->priv; - - while (readl(&adap_mdio->useraccess0) & MDIO_USERACCESS0_GO) - ; - - writel(MDIO_USERACCESS0_GO | MDIO_USERACCESS0_WRITE_WRITE | - ((reg & 0x1f) << 21) | ((addr & 0x1f) << 16) | - (val & 0xffff), &adap_mdio->useraccess0); - - /* Wait for command to complete */ - while (readl(&adap_mdio->useraccess0) & MDIO_USERACCESS0_GO) - ; - - return 0; -} - static void __attribute__((unused)) keystone2_eth_gigabit_enable(struct udevice *dev) { struct ks2_eth_priv *priv = dev_get_priv(dev); - u_int16_t data; - - if (priv->has_mdio) { - data = keystone2_mdio_read(priv->mdio_bus, priv->phy_addr, - MDIO_DEVAD_NONE, 0); - /* speed selection MSB */ - if (!(data & (1 << 6))) - return; - } /* * Check if link detected is giga-bit * If Gigabit mode detected, enable gigbit in MAC */ + if (priv->has_mdio) { + if (priv->phydev->speed != 1000) + return; + } + writel(readl(DEVICE_EMACSL_BASE(priv->slave_port - 1) + CPGMACSL_REG_CTL) | EMAC_MACCONTROL_GIGFORCE | EMAC_MACCONTROL_GIGABIT_ENABLE, @@ -484,8 +413,6 @@ static int ks2_eth_start(struct udevice *dev) hw_config_streaming_switch(); if (priv->has_mdio) { - keystone2_mdio_reset(priv->mdio_bus); - phy_startup(priv->phydev); if (priv->phydev->link == 0) { pr_err("phy startup failed\n"); @@ -605,9 +532,9 @@ static int ks2_eth_probe(struct udevice *dev) { struct ks2_eth_priv *priv = dev_get_priv(dev); struct mii_dev *mdio_bus; - int ret; priv->dev = dev; + priv->emac_open = false; /* These clock enables has to be moved to common location */ if (cpu_is_k2g()) @@ -626,45 +553,36 @@ static int ks2_eth_probe(struct udevice *dev) if (cpu_is_k2e() || cpu_is_k2l()) pll_pa_clk_sel(); - priv->net_rx_buffs.buff_ptr = rx_buffs; priv->net_rx_buffs.num_buffs = RX_BUFF_NUMS; priv->net_rx_buffs.buff_len = RX_BUFF_LEN; if (priv->slave_port == 1) { +#ifndef CONFIG_SOC_K2G + keystone2_net_serdes_setup(); +#endif /* * Register MDIO bus for slave 0 only, other slave have * to re-use the same */ - mdio_bus = mdio_alloc(); + mdio_bus = cpsw_mdio_init("ethernet-mdio", + (u32)priv->mdio_base, + EMAC_MDIO_CLOCK_FREQ, + EMAC_MDIO_BUS_FREQ); if (!mdio_bus) { pr_err("MDIO alloc failed\n"); return -ENOMEM; } priv->mdio_bus = mdio_bus; - mdio_bus->read = keystone2_mdio_read; - mdio_bus->write = keystone2_mdio_write; - mdio_bus->reset = keystone2_mdio_reset; - mdio_bus->priv = priv->mdio_base; - sprintf(mdio_bus->name, "ethernet-mdio"); - - ret = mdio_register(mdio_bus); - if (ret) { - pr_err("MDIO bus register failed\n"); - return ret; - } } else { /* Get the MDIO bus from slave 0 device */ struct ks2_eth_priv *parent_priv; parent_priv = dev_get_priv(dev->parent); priv->mdio_bus = parent_priv->mdio_bus; + priv->mdio_base = parent_priv->mdio_base; } -#ifndef CONFIG_SOC_K2G - keystone2_net_serdes_setup(); -#endif - priv->netcp_pktdma = &netcp_pktdma; if (priv->has_mdio) { @@ -680,9 +598,7 @@ int ks2_eth_remove(struct udevice *dev) { struct ks2_eth_priv *priv = dev_get_priv(dev); - free(priv->phydev); - mdio_unregister(priv->mdio_bus); - mdio_free(priv->mdio_bus); + cpsw_mdio_free(priv->mdio_bus); return 0; }