From patchwork Fri Sep 21 00:22:14 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 147179 Delivered-To: patch@linaro.org Received: by 2002:a2e:1648:0:0:0:0:0 with SMTP id 8-v6csp169136ljw; Thu, 20 Sep 2018 17:39:04 -0700 (PDT) X-Google-Smtp-Source: ANB0VdbHcXiLmH7aRRclDLBtSQW2ThVnMSqvHep78IT2wPPsuh78r75qUUfFd1SFc3vsbFz0XCiI X-Received: by 2002:aa7:c60d:: with SMTP id h13-v6mr8203198edq.9.1537490344012; Thu, 20 Sep 2018 17:39:04 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1537490344; cv=none; d=google.com; s=arc-20160816; b=GxCAhrQbX+u/Uta6F0GbcVW+DjhEY++gtfuCs1YWIiV2PwOODP5iGHd0MB9ReJjXiE mXsLSO9OPBms7kSThJNoA5Wl201TNr4zCLz6CIZKEZG2Lo3FsbUfCUFeaDVZKGE9if3N BxCnpI6kwucqhe4mV0DN4B6IlCQXrA037OkmDXyhP03QaTbZXMp5nabzXSmo+wxR3K2N 4g26NkYnVVAqXTCUk0DwL5m8tw9gxKcBrJJfSms/Z88K0q6OOLtY3mG9E+RdA79m+7dQ bXqP5lpnnXe8Ap9iskSe6ABvO1MdDNNn26QKl8Ox/9CklSyC4H7lM2qEvy9Ts22A8H6A 8IrA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:cc:references:in-reply-to:message-id :date:to:from:dkim-signature; bh=/X3Xf+1NhmAjWWTuyBJ8pOixMfXsXykD5ZZvF1OxmUc=; b=Zif4536KkznTnF5jx+um2T5W6l/6VD12jmg7Jom2FjaVNKOG+3y+n63WVU2eiMLgkT Hc/55nEs6F8RjUmJYbdfCTveMrASvzILAliYK2cFOru494aBWyx1OQujUUTajXLgSBwK GiLmrsJiopLqO0keRcMmvGujC9pQrgLU1eak+hO/G2h5mK4bL0BXbEL0CnMInE1/gy1p mSKkKZZenwudSSlooBsAZtK55+HVXRMfNQ55rjf1nhVxfOJsKxzR6sv8rvk/rkV38GU/ sFryo2B9Q1gGcHUeRVHZLadFF+R4IDY83zLU1g+RNuqYtmhdCzT4sdVmQDayE+ru560T QEKA== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=ggNnuYIe; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.denx.de (dione.denx.de. [81.169.180.215]) by mx.google.com with ESMTP id c1-v6si3316615edn.411.2018.09.20.17.39.03; Thu, 20 Sep 2018 17:39:04 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=ggNnuYIe; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: by lists.denx.de (Postfix, from userid 105) id 97C9CC21E12; Fri, 21 Sep 2018 00:39:03 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED, RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id C99DAC21E35; Fri, 21 Sep 2018 00:22:38 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id E894BC21E2F; Fri, 21 Sep 2018 00:22:37 +0000 (UTC) Received: from mail-io1-f67.google.com (mail-io1-f67.google.com [209.85.166.67]) by lists.denx.de (Postfix) with ESMTPS id CFDAAC21C38 for ; Fri, 21 Sep 2018 00:22:33 +0000 (UTC) Received: by mail-io1-f67.google.com with SMTP id n18-v6so10446671ioa.9 for ; Thu, 20 Sep 2018 17:22:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=3CJfhqOM1ntrsw/V+lkBWRm7AZRba4JEZ4TFYRC94K8=; b=ggNnuYIen7qGs0RdwEVcAu0oahhIzdp7gRr1vwDlwt4oK2ju6oWXZQ5CXn8UF4DL9d a+IUpYR5rIjwSZ+MhYn2JZ5gkAqg17mLenNAxI2LFB6h3HOLdS0dDdyzs769n/aip7lF ucxUGQfm3vn69ESl6o7MpQ/ybYWhhvgasYntA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=3CJfhqOM1ntrsw/V+lkBWRm7AZRba4JEZ4TFYRC94K8=; b=As4SLgSdYFuZWwNPDlz53U6lGZ7n3jskI14waqPsL46P1UAFVp9dOqJUIGdfcde1Ad HUHHIIEVR27KYKkpPECR2Hw56OEWj8VuuVKL8k4kQJK+O1WVkinPCzrJVDO1wmKlQM+0 GlKGoitmkg7esQVIJTgQeRm2Dn+W0gIyBCxgqv6lVh27USj98FiJOZiA9zXJjzFZQz6o zHr1EyciBzmb8V8Jygyf7jhNYUXAcZVUTZpqg2LuXuYPuMX1N7tjSkypWyrZ0PTMdd+2 bxidhINEbq4uLAz0EnWNGQvCCEMFnaW3IXh0Y1Zxm/sKUEAe7yoWw24wuK/v23n+NTDY CWZA== X-Gm-Message-State: ABuFfoi0VvanIYrDPEKdg9xsarGcFKzbLNbqwndoHC5KgW4DmKl4O34Y F53AhbIC5cUDPZ8Bs6k3qhroqtSs3kWA X-Received: by 2002:a6b:7416:: with SMTP id s22-v6mr6146939iog.89.1537489352185; Thu, 20 Sep 2018 17:22:32 -0700 (PDT) Received: from localhost.localdomain ([209.82.80.116]) by smtp.gmail.com with ESMTPSA id l186-v6sm1423274ith.42.2018.09.20.17.22.30 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 20 Sep 2018 17:22:31 -0700 (PDT) From: Manivannan Sadhasivam To: sjg@chromium.org, philipp.tomsich@theobroma-systems.com Date: Thu, 20 Sep 2018 17:22:14 -0700 Message-Id: <20180921002215.2013-4-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180921002215.2013-1-manivannan.sadhasivam@linaro.org> References: <20180921002215.2013-1-manivannan.sadhasivam@linaro.org> Cc: tom@vamrs.com, amit.kucheria@linaro.org, dev@vamrs.com, u-boot@lists.denx.de, Manivannan Sadhasivam , stephen@vamrs.com Subject: [U-Boot] [PATCH v2 3/4] rockchip: rk3399: Add Rock960 CE board support X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Add board support for Rock960 CE board from Vamrs. This board utilizes common Rock960 family support. Following peripherals are tested and known to work: * USB 2.0 * MMC This commit also adds DDR configuration for LPDDR3-2GiB-1600MHz which is being used on the board. Signed-off-by: Manivannan Sadhasivam --- Changes in v2: * Added missing config options for USB/uSD * Fixed the commit description for DDR speed arch/arm/dts/Makefile | 1 + arch/arm/dts/rk3399-rock960.dts | 45 + .../arm/dts/rk3399-sdram-lpddr3-2GB-1600.dtsi | 1536 +++++++++++++++++ configs/rock960-rk3399_defconfig | 67 + 4 files changed, 1649 insertions(+) create mode 100644 arch/arm/dts/rk3399-rock960.dts create mode 100644 arch/arm/dts/rk3399-sdram-lpddr3-2GB-1600.dtsi create mode 100644 configs/rock960-rk3399_defconfig diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index ebfa2272627..9b891826b73 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -51,6 +51,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \ rk3399-puma-ddr1333.dtb \ rk3399-puma-ddr1600.dtb \ rk3399-puma-ddr1866.dtb \ + rk3399-rock960.dtb \ rv1108-evb.dtb dtb-$(CONFIG_ARCH_MESON) += \ meson-gxbb-nanopi-k2.dtb \ diff --git a/arch/arm/dts/rk3399-rock960.dts b/arch/arm/dts/rk3399-rock960.dts new file mode 100644 index 00000000000..25c58b42611 --- /dev/null +++ b/arch/arm/dts/rk3399-rock960.dts @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Manivannan Sadhasivam + */ + +/dts-v1/; +#include "rk3399-rock960.dtsi" +#include "rk3399-sdram-lpddr3-2GB-1600.dtsi" + +/ { + model = "96boards Rock960"; + compatible = "vamrs,rock960", "rockchip,rk3399"; + + chosen { + stdout-path = "serial2:1500000n8"; + }; +}; + +&pcie0 { + ep-gpios = <&gpio2 RK_PA2 GPIO_ACTIVE_HIGH>; +}; + +&pinctrl { + pcie { + pcie_drv: pcie-drv { + rockchip,pins = + <2 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb2 { + host_vbus_drv: host-vbus-drv { + rockchip,pins = + <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&vcc3v3_pcie { + gpio = <&gpio2 5 GPIO_ACTIVE_HIGH>; +}; + +&vcc5v0_host { + gpio = <&gpio4 25 GPIO_ACTIVE_HIGH>; +}; diff --git a/arch/arm/dts/rk3399-sdram-lpddr3-2GB-1600.dtsi b/arch/arm/dts/rk3399-sdram-lpddr3-2GB-1600.dtsi new file mode 100644 index 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a/configs/rock960-rk3399_defconfig b/configs/rock960-rk3399_defconfig new file mode 100644 index 00000000000..9c6db64d7ec --- /dev/null +++ b/configs/rock960-rk3399_defconfig @@ -0,0 +1,67 @@ +CONFIG_ARM=y +CONFIG_ARCH_ROCKCHIP=y +CONFIG_SYS_TEXT_BASE=0x00200000 +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x4000 +CONFIG_ROCKCHIP_RK3399=y +CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x4000 +CONFIG_TARGET_ROCK960_RK3399=y +CONFIG_DEBUG_UART_BASE=0xFF1A0000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_BAUDRATE=1500000 +CONFIG_SPL_STACK_R_ADDR=0x80000 +CONFIG_DEFAULT_DEVICE_TREE="rk3399-rock960" +CONFIG_DEBUG_UART=y +CONFIG_FIT=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.py" +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock960.dtb" +CONFIG_SYS_PROMPT="rock960 => " +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000 +CONFIG_SPL_ATF=y +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_TIME=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_REGMAP=y +CONFIG_SPL_REGMAP=y +CONFIG_SYSCON=y +CONFIG_SPL_SYSCON=y +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_ROCKCHIP_RK3399=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_RK8XX=y +CONFIG_REGULATOR_PWM=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_RAM=y +CONFIG_SPL_RAM=y +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_STORAGE=y +CONFIG_USE_TINY_PRINTF=y +CONFIG_ERRNO_STR=y