From patchwork Tue Jun 12 20:24:10 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nishanth Menon X-Patchwork-Id: 138378 Delivered-To: patch@linaro.org Received: by 2002:a2e:970d:0:0:0:0:0 with SMTP id r13-v6csp5813915lji; Tue, 12 Jun 2018 13:25:20 -0700 (PDT) X-Google-Smtp-Source: ADUXVKJdIo8L0xgX3W2qmAOGjzIjJR2sT/DlwDdrU7uSOkkm3XBs8/atHmYDyhlFct/RyLjVZUfL X-Received: by 2002:adf:f40a:: with SMTP id g10-v6mr1721109wro.256.1528835120026; Tue, 12 Jun 2018 13:25:20 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1528835120; cv=none; d=google.com; s=arc-20160816; b=vpjBL950122KugMpiCxInzsoAfEpnt41B3bUxIV84SsalKRnbbcHDzpvHQZbnpmbOf WBII37szWulyg+sKcH2NOuoPM76/moCkKK9capBEOdIZBROd5WzBPCG356jxIwaBYqOX P3kJyMPdviXyraobpB6LQ1sFZTdeN8CpJkKh8kpjEZ1gfzHAuKlXRvDNzL/QrZ1q8ZI1 Y38quMcu9d7AessFjRSMrhlYRSC4khfTdJbur8lebT/XsogKEDpcrQBHeb3P2/0Hz1g2 H7y8A1RVilLG/g1yOr4RKExfI2UXiHV5oSXGSxDfP8ZV8rvgWQu2QbcUNsPYFymAp4Uy W0Yg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:list-subscribe:list-help :list-post:list-archive:list-unsubscribe:list-id:precedence:subject :cc:mime-version:references:in-reply-to:message-id:date:to:from :dkim-signature:arc-authentication-results; bh=y/0kg7iVLPUAULGH61jqaNy5dNIW37KLF8+Lc3uY0vQ=; b=ZrdHJtauvHzctlk7L+5P7b+R51xlWpmZ46RGQ994YHi5JuRI8K+Y2JlDcY9RDCNJeI i15pJZvAzBDfipn3UUx3qY0WZpV/IJYe+3+W20pxftf9b4GvgXLHt6dIglMqiqvQdLvM T+ygKkQJAGuhnSWmGlvJualPFd/SjGKIyvoJ9xoeRgv8u7vQug63oeS+KGCwdODMMY2Z ogvBaEubnqsMjC1SnZi0p1kiU/uHoBoUFmh85+LPXs3OfJ3h9577doB5HxQYDbDbgz7Y KhdW9I7nUUM4yDA4x8FD+JoySttZmG/n+rOTFu1WPIZU3ZdibUFAtEI1wYN8ajk1bu8l ietg== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=s+Vj+Udo; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=QUARANTINE sp=NONE dis=QUARANTINE) header.from=ti.com Return-Path: Received: from lists.denx.de (dione.denx.de. [81.169.180.215]) by mx.google.com with ESMTP id m62-v6si1359418ede.199.2018.06.12.13.25.19; Tue, 12 Jun 2018 13:25:20 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=s+Vj+Udo; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=QUARANTINE sp=NONE dis=QUARANTINE) header.from=ti.com Received: by lists.denx.de (Postfix, from userid 105) id 6EC6AC21DB5; Tue, 12 Jun 2018 20:24:59 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=KHOP_BIG_TO_CC, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id D5F07C21D83; Tue, 12 Jun 2018 20:24:39 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id F10ABC21BE5; Tue, 12 Jun 2018 20:24:36 +0000 (UTC) Received: from fllnx209.ext.ti.com (fllnx209.ext.ti.com [198.47.19.16]) by lists.denx.de (Postfix) with ESMTPS id D7416C21BE5 for ; Tue, 12 Jun 2018 20:24:34 +0000 (UTC) Received: from dflxv15.itg.ti.com ([128.247.5.124]) by fllnx209.ext.ti.com (8.15.1/8.15.1) with ESMTP id w5CKOD3e026499; Tue, 12 Jun 2018 15:24:13 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1528835053; bh=dPREojNimxFYzgI3MQVg/7rR0UCE1nimJv6wY+3A9pA=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=s+Vj+Udo/VBTZvuX+gBJtuzoAsg46PmXfsOBsoYANCda251cs/+EOU8W+5YIpfGHI yiamPDXzxQKfuG2CA7jkcV7eWSbilqaluROSX/HehDek0yGe56gEdGGeybcCC/tqxd I6N68Xis9zAI0NyGL1RTC1yaEFlcy/Yvj8S10q1U= Received: from DLEE104.ent.ti.com (dlee104.ent.ti.com [157.170.170.34]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id w5CKOD8F008045; Tue, 12 Jun 2018 15:24:13 -0500 Received: from DLEE106.ent.ti.com (157.170.170.36) by DLEE104.ent.ti.com (157.170.170.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1466.3; Tue, 12 Jun 2018 15:24:13 -0500 Received: from dflp32.itg.ti.com (10.64.6.15) by DLEE106.ent.ti.com (157.170.170.36) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1466.3 via Frontend Transport; Tue, 12 Jun 2018 15:24:13 -0500 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id w5CKODq9025717; Tue, 12 Jun 2018 15:24:13 -0500 From: Nishanth Menon To: Tom Rini , Russell King , Marc Zyngier , Catalin Marinas , Will Deacon , Tony Lindgren Date: Tue, 12 Jun 2018 15:24:10 -0500 Message-ID: <20180612202411.29798-4-nm@ti.com> X-Mailer: git-send-email 2.15.1 In-Reply-To: <20180612202411.29798-1-nm@ti.com> References: <20180612202411.29798-1-nm@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Cc: Ard Biesheuvel , Andre Przywara , U-Boot-Denx , Robin Murphy , linux-arm-kernel@lists.infradead.org Subject: [U-Boot] [PATCH 3/4] ARM: mach-omap2: omap5/dra7: Enable ACTLR[0] (Enable invalidates of BTB) to facilitate CVE_2017-5715 WA in OS X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Enable CVE_2017_5715 and since we have our own v7_arch_cp15_set_acr function to setup the bits, we are able to override the settings. Without this enabled, Linux kernel reports: CPU0: Spectre v2: firmware did not set auxiliary control register IBE bit, system vulnerable With this enabled, Linux kernel reports: CPU0: Spectre v2: using ICIALLU workaround NOTE: This by itself does not enable the workaround for CPU1 (on OMAP5 and DRA72/AM572 SoCs) and may require additional kernel patches. Signed-off-by: Nishanth Menon --- arch/arm/mach-omap2/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig index 3bb1ecb58de0..77820cc8d1e4 100644 --- a/arch/arm/mach-omap2/Kconfig +++ b/arch/arm/mach-omap2/Kconfig @@ -53,6 +53,7 @@ config OMAP54XX bool "OMAP54XX SoC" select ARM_ERRATA_798870 select SYS_THUMB_BUILD + select ARM_CORTEX_A15_CVE_2017_5715 imply NAND_OMAP_ELM imply NAND_OMAP_GPMC imply SPL_DISPLAY_PRINT