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[81.169.180.215]) by mx.google.com with ESMTP id z38-v6si1753347edb.261.2018.06.11.08.53.42; Mon, 11 Jun 2018 08:53:43 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=L1SsYDWx; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: by lists.denx.de (Postfix, from userid 105) id A25E0C21D74; Mon, 11 Jun 2018 15:51:07 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=KHOP_BIG_TO_CC, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 5182EC21CB1; Mon, 11 Jun 2018 15:50:54 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id B8203C21DAF; Mon, 11 Jun 2018 15:50:45 +0000 (UTC) Received: from mail-pl0-f68.google.com (mail-pl0-f68.google.com [209.85.160.68]) by lists.denx.de (Postfix) with ESMTPS id 5020FC21D8A for ; Mon, 11 Jun 2018 15:50:41 +0000 (UTC) Received: by mail-pl0-f68.google.com with SMTP id t12-v6so12550030plo.7 for ; Mon, 11 Jun 2018 08:50:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=f/1fdxVAA0aTSFOpliNxb0P9mrDViKV0R/4zJaQgJ9k=; b=L1SsYDWx6eojhki10Jmd3sOJhUJu1YLED7byH6jU6SI4JHl1QucVfzUOSMhaHhoA8Y ckbVRpvy34yO7/NQ611DfOpkrB9dFYeXrsCbKkaW8QOlGvfpvVU+pMvLz342DfqUNLc/ xxhLT75yf9zvB7NKcE/xth/zVvMuWXn+ivG3s= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=f/1fdxVAA0aTSFOpliNxb0P9mrDViKV0R/4zJaQgJ9k=; b=AoSaYyhJsNSz+qxrr0ABGsreEnTqtmHGtTmWFyYvnOGmW8YeIZdF20b4ERTONvWgsT 0ZMX8IqS2mvRX3fJzkPiB1CVsSXk8BqE9r6j2zVhOHwO2nZ2Y2M98Xq5F7a+lBRWA+NS K5E32AnurX2bWuw2rDFuSyJKbIgIiVAiFcNmTytCiO40yNlrtn3BROmis1f+T2n5QWgC cg42q4prh0oTz2WCHeDdC2NLqww3hUfynzwwUkRz2GLLRDrEVsUlQVSTlqSvHIuukDvK EISSkR0NbJt66uk1+MrQiTZd8p68m606yX7ZZX+GECOmIhNGiievVYZWzz8sco6SYWtm Isfw== X-Gm-Message-State: APt69E2hKdpyxVzBzHgWVS+Pb7dIAmO57oh/NAXUePZTRiJcZpFmjUOC jQAk6vrNtFFDkC/cUbqOVMei X-Received: by 2002:a17:902:c85:: with SMTP id 5-v6mr12807347plt.126.1528732239838; Mon, 11 Jun 2018 08:50:39 -0700 (PDT) Received: from localhost.localdomain ([2405:204:7288:73c5:d4c6:ffd5:c258:b7e0]) by smtp.gmail.com with ESMTPSA id s1-v6sm31638261pgv.48.2018.06.11.08.50.31 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 11 Jun 2018 08:50:39 -0700 (PDT) From: Manivannan Sadhasivam To: albert.u.boot@aribaud.net, sjg@chromium.org, marek.vasut+renesas@gmail.com, u-boot@lists.denx.de Date: Mon, 11 Jun 2018 21:18:31 +0530 Message-Id: <20180611154832.3251-9-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180611154832.3251-1-manivannan.sadhasivam@linaro.org> References: <20180611154832.3251-1-manivannan.sadhasivam@linaro.org> Cc: daniel.thompson@linaro.org, manivannanece23@gmail.com, bdong@ucrobotics.com, thomas.liau@actions-semi.com, hzhang@ucrobotics.com, amit.kucheria@linaro.org, liuwei@actions-semi.com, afaerber@suse.de, jeff.chen@actions-semi.com, mp-cs@actions-semi.com Subject: [U-Boot] [RESEND][PATCH 8/9] serial: Add Actions Semi OWL UART support X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This commit adds Actions Semi OWL family UART support. This driver relies on baudrate configured by primary bootloaders. Signed-off-by: Manivannan Sadhasivam --- drivers/serial/Kconfig | 8 +++ drivers/serial/Makefile | 1 + drivers/serial/serial_owl.c | 136 ++++++++++++++++++++++++++++++++++++ 3 files changed, 145 insertions(+) create mode 100644 drivers/serial/serial_owl.c diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index 2940bd05dc..766e5ced03 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -625,6 +625,14 @@ config MSM_SERIAL for example APQ8016 and MSM8916. Single baudrate is supported in current implementation (115200). +config OWL_SERIAL + bool "Actions Semi OWL UART" + depends on DM_SERIAL && ARCH_OWL + help + If you have a Actions Semi OWL based board and want to use the on-chip + serial port, say Y to this option. If unsure, say N. + Single baudrate is supported in current implementation (115200). + config PXA_SERIAL bool "PXA serial port support" help diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index e66899489e..9fa81d855d 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -64,6 +64,7 @@ obj-$(CONFIG_MSM_SERIAL) += serial_msm.o obj-$(CONFIG_MVEBU_A3700_UART) += serial_mvebu_a3700.o obj-$(CONFIG_MPC8XX_CONS) += serial_mpc8xx.o obj-$(CONFIG_NULLDEV_SERIAL) += serial_nulldev.o +obj-$(CONFIG_OWL_SERIAL) += serial_owl.o ifndef CONFIG_SPL_BUILD obj-$(CONFIG_USB_TTY) += usbtty.o diff --git a/drivers/serial/serial_owl.c b/drivers/serial/serial_owl.c new file mode 100644 index 0000000000..6fd97e2502 --- /dev/null +++ b/drivers/serial/serial_owl.c @@ -0,0 +1,136 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Actions Semi OWL SoCs UART driver + * + * Copyright (C) 2015 Actions Semi Co., Ltd. + * Copyright (C) 2018 Manivannan Sadhasivam + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +/* UART Registers */ +#define OWL_UART_CTL (0x0000) +#define OWL_UART_RXDAT (0x0004) +#define OWL_UART_TXDAT (0x0008) +#define OWL_UART_STAT (0x000C) + +/* UART_CTL Register Definitions */ +#define OWL_UART_CTL_PRS_NONE GENMASK(6, 4) +#define OWL_UART_CTL_STPS BIT(2) +#define OWL_UART_CTL_DWLS 3 + +/* UART_STAT Register Definitions */ +#define OWL_UART_STAT_TFES BIT(10) /* TX FIFO Empty Status */ +#define OWL_UART_STAT_RFFS BIT(9) /* RX FIFO full Status */ +#define OWL_UART_STAT_TFFU BIT(6) /* TX FIFO full Status */ +#define OWL_UART_STAT_RFEM BIT(5) /* RX FIFO Empty Status */ + +struct owl_serial_priv { + phys_addr_t base; +}; + +int owl_serial_setbrg(struct udevice *dev, int baudrate) +{ + /* Driver supports only fixed baudrate */ + return 0; +} + +static int owl_serial_getc(struct udevice *dev) +{ + struct owl_serial_priv *priv = dev_get_priv(dev); + + if (readl(priv->base + OWL_UART_STAT) & OWL_UART_STAT_RFEM) + return -EAGAIN; + + return (int)(readl(priv->base + OWL_UART_RXDAT)); +} + +static int owl_serial_putc(struct udevice *dev, const char ch) +{ + struct owl_serial_priv *priv = dev_get_priv(dev); + + if (readl(priv->base + OWL_UART_STAT) & OWL_UART_STAT_TFFU) + return -EAGAIN; + + writel(ch, priv->base + OWL_UART_TXDAT); + + return 0; +} + +static int owl_serial_pending(struct udevice *dev, bool input) +{ + struct owl_serial_priv *priv = dev_get_priv(dev); + unsigned int stat = readl(priv->base + OWL_UART_STAT); + + if (input) + return !(stat & OWL_UART_STAT_RFEM); + else + return !(stat & OWL_UART_STAT_TFES); +} + +static int owl_serial_probe(struct udevice *dev) +{ + struct owl_serial_priv *priv = dev_get_priv(dev); + struct clk clk; + u32 uart_ctl; + int ret; + + /* Set data, parity and stop bits */ + uart_ctl = readl(priv->base + OWL_UART_CTL); + uart_ctl &= ~(OWL_UART_CTL_PRS_NONE); + uart_ctl &= ~(OWL_UART_CTL_STPS); + uart_ctl |= OWL_UART_CTL_DWLS; + writel(uart_ctl, priv->base + OWL_UART_CTL); + + /* Enable UART clock */ + ret = clk_get_by_index(dev, 0, &clk); + if (ret < 0) + return ret; + + ret = clk_enable(&clk); + if (ret < 0) + return ret; + + return 0; +} + +static int owl_serial_ofdata_to_platdata(struct udevice *dev) +{ + struct owl_serial_priv *priv = dev_get_priv(dev); + + priv->base = dev_read_addr(dev); + if (priv->base == FDT_ADDR_T_NONE) + return -EINVAL; + + return 0; +} + +static const struct dm_serial_ops owl_serial_ops = { + .putc = owl_serial_putc, + .pending = owl_serial_pending, + .getc = owl_serial_getc, + .setbrg = owl_serial_setbrg, +}; + +static const struct udevice_id owl_serial_ids[] = { + { .compatible = "actions,s900-serial" }, + { } +}; + +U_BOOT_DRIVER(serial_owl) = { + .name = "serial_owl", + .id = UCLASS_SERIAL, + .of_match = owl_serial_ids, + .ofdata_to_platdata = owl_serial_ofdata_to_platdata, + .priv_auto_alloc_size = sizeof(struct owl_serial_priv), + .probe = owl_serial_probe, + .ops = &owl_serial_ops, + .flags = DM_FLAG_PRE_RELOC, +};