From patchwork Thu Apr 19 15:49:16 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexander Graf X-Patchwork-Id: 133833 Delivered-To: patch@linaro.org Received: by 10.46.66.142 with SMTP id h14csp791291ljf; Thu, 19 Apr 2018 08:52:37 -0700 (PDT) X-Google-Smtp-Source: AIpwx4/k/Pu7/dYnHc3DOlQuKB/YxXcy+fsDHRPLpmVqfu+oAwhtlw7QPNIvslnBd6FEB5NzYk59 X-Received: by 10.80.184.10 with SMTP id j10mr9326471ede.272.1524153157804; Thu, 19 Apr 2018 08:52:37 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1524153157; cv=none; d=google.com; s=arc-20160816; b=VDbv914Z5TuRmWfQukluehT6vi+4Z7za1QZNtehV5oEEsGTc8UmgWtc3PSgn4nB/B3 LK8YkcG6Ww8Qx5NO1s61sZzdD+JxsinhtdslSjhb9jd6fyxgypRAf/Gf7hpKW79GHLpq lqhG68dshibTC71Sr1hp0RCnC3W4h4ZGANrGBB7POFdWMl7kKFA3Cf82kw/g6BLuqNSd NNoTW/Kdi2/Cx5OqS5AzkgB3zUzrmE+iYhlkQ2EPRxbXg66JItSMb0btnvThdXkdOTqM CmCrQJfkJ8Qa07+8lBqC299//YgBqaOOmTC5VdBEexxyGDOH4tsGg/1t3R+Z5euFiocV TJBg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:cc:references:in-reply-to:message-id :date:to:from:arc-authentication-results; bh=z0MZGJsQL0BFtqW+Je/b/FhRDWjoAwmbPgDDAUCb0so=; b=bQDrYHoPlVWevlBw/2BCyXuojYF3AFgOKzo9OivcA3KwtqkYkgMgva1YGuXt8kMbNZ xWdV9AcRMBbTTTYqbLHaeJ1UmtF5TJj6uep2pA7+e/qQWht+kipYXEodZn5PRgsgXriI tHNuVCAQ9g/o/M5D/4Yr4VWfbKdsFgpn//9YLzYCOS6030FcOfy97J5ga4BK9+GVhoX6 chWt40CZOrAk46IbYXlgykkiCgIrOsBRBGQkbm2TqLcjH0VFyu2TG3qodQmo/JnHyhzp qvoJM4whkLPgN9CT4yXbqxPyMtLygxgubb/pfi0Lio9YwIJXuf8Q8SDg9jSOoblIqBkD Yw7Q== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Return-Path: Received: from lists.denx.de (dione.denx.de. [81.169.180.215]) by mx.google.com with ESMTP id g3si1022789edd.382.2018.04.19.08.52.37; Thu, 19 Apr 2018 08:52:37 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by lists.denx.de (Postfix, from userid 105) id 33BA5C21E89; Thu, 19 Apr 2018 15:50:41 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 0C310C21FF6; Thu, 19 Apr 2018 15:49:33 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id D563DC21D8A; Thu, 19 Apr 2018 15:49:26 +0000 (UTC) Received: from mx2.suse.de (mx2.suse.de [195.135.220.15]) by lists.denx.de (Postfix) with ESMTPS id BC302C21F91 for ; Thu, 19 Apr 2018 15:49:25 +0000 (UTC) X-Virus-Scanned: by amavisd-new at test-mx.suse.de Received: from relay1.suse.de (charybdis-ext.suse.de [195.135.220.254]) by mx2.suse.de (Postfix) with ESMTP id 278CBAF80; Thu, 19 Apr 2018 15:49:25 +0000 (UTC) From: Alexander Graf To: u-boot@lists.denx.de Date: Thu, 19 Apr 2018 17:49:16 +0200 Message-Id: <20180419154923.70719-2-agraf@suse.de> X-Mailer: git-send-email 2.12.3 In-Reply-To: <20180419154923.70719-1-agraf@suse.de> References: <20180419154923.70719-1-agraf@suse.de> Cc: Heinrich Schuchardt , schwab@suse.de, Greentime Hu Subject: [U-Boot] [PATCH v2 1/8] riscv: Add setjmp/longjmp code X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" To support efi_loader we need to have platform support for setjmp/longjmp. Add it here. Signed-off-by: Alexander Graf --- v1 -> v2: - Allow 32bit target - Also save/restore ra, sp --- arch/riscv/include/asm/setjmp.h | 26 ++++++++++++++++ arch/riscv/lib/Makefile | 1 + arch/riscv/lib/setjmp.S | 66 +++++++++++++++++++++++++++++++++++++++++ 3 files changed, 93 insertions(+) create mode 100644 arch/riscv/include/asm/setjmp.h create mode 100644 arch/riscv/lib/setjmp.S diff --git a/arch/riscv/include/asm/setjmp.h b/arch/riscv/include/asm/setjmp.h new file mode 100644 index 0000000000..01ad6d081f --- /dev/null +++ b/arch/riscv/include/asm/setjmp.h @@ -0,0 +1,26 @@ +/* + * (C) Copyright 2018 Alexander Graf + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _SETJMP_H_ +#define _SETJMP_H_ 1 + +/* + * This really should be opaque, but the EFI implementation wrongly + * assumes that a 'struct jmp_buf_data' is defined. + */ +struct jmp_buf_data { + /* x2, x8, x9, x18, x19, x20, x21, x22, x23, x24, x25, x26, x27, sp */ + unsigned long s_regs[12]; /* s0 - s11 */ + unsigned long ra; + unsigned long sp; +}; + +typedef struct jmp_buf_data jmp_buf[1]; + +int setjmp(jmp_buf jmp); +void longjmp(jmp_buf jmp, int ret); + +#endif /* _SETJMP_H_ */ diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile index 323cf3e835..6d97aa2719 100644 --- a/arch/riscv/lib/Makefile +++ b/arch/riscv/lib/Makefile @@ -12,3 +12,4 @@ obj-$(CONFIG_CMD_BOOTM) += bootm.o obj-$(CONFIG_CMD_GO) += boot.o obj-y += cache.o obj-y += interrupts.o +obj-y += setjmp.o diff --git a/arch/riscv/lib/setjmp.S b/arch/riscv/lib/setjmp.S new file mode 100644 index 0000000000..103f359185 --- /dev/null +++ b/arch/riscv/lib/setjmp.S @@ -0,0 +1,66 @@ +/* + * (C) 2018 Alexander Graf + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +#ifdef CONFIG_CPU_RISCV_64 +#define STORE_IDX(reg, idx) sd reg, (idx*8)(a0) +#define LOAD_IDX(reg, idx) ld reg, (idx*8)(a0) +#else +#define STORE_IDX(reg, idx) sw reg, (idx*4)(a0) +#define LOAD_IDX(reg, idx) lw reg, (idx*4)(a0) +#endif + +.pushsection .text.setjmp, "ax" +ENTRY(setjmp) + /* Preserve all callee-saved registers and the SP */ + STORE_IDX(s0, 0) + STORE_IDX(s1, 1) + STORE_IDX(s2, 2) + STORE_IDX(s3, 3) + STORE_IDX(s4, 4) + STORE_IDX(s5, 5) + STORE_IDX(s6, 6) + STORE_IDX(s7, 7) + STORE_IDX(s8, 8) + STORE_IDX(s9, 9) + STORE_IDX(s10, 10) + STORE_IDX(s11, 11) + STORE_IDX(ra, 12) + STORE_IDX(sp, 13) + li a0, 0 + ret +ENDPROC(setjmp) +.popsection + +.pushsection .text.longjmp, "ax" +ENTRY(longjmp) + LOAD_IDX(s0, 0) + LOAD_IDX(s1, 1) + LOAD_IDX(s2, 2) + LOAD_IDX(s3, 3) + LOAD_IDX(s4, 4) + LOAD_IDX(s5, 5) + LOAD_IDX(s6, 6) + LOAD_IDX(s7, 7) + LOAD_IDX(s8, 8) + LOAD_IDX(s9, 9) + LOAD_IDX(s10, 10) + LOAD_IDX(s11, 11) + LOAD_IDX(ra, 12) + LOAD_IDX(sp, 13) + + /* Move the return value in place, but return 1 if passed 0. */ + beq a1, zero, longjmp_1 + mv a0, a1 + ret + + longjmp_1: + li a0, 1 + ret +ENDPROC(longjmp) +.popsection