From patchwork Thu Apr 12 13:41:56 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexander Graf X-Patchwork-Id: 133277 Delivered-To: patch@linaro.org Received: by 10.46.84.29 with SMTP id i29csp1700961ljb; Thu, 12 Apr 2018 06:43:11 -0700 (PDT) X-Google-Smtp-Source: AIpwx480J+OTKKXcTt17r0U5VkEBwctkh9nEmk/1A4SujYU0hYhT1jvorGr2OxmxjD5iTk/vFGfU X-Received: by 10.80.177.81 with SMTP id l17mr15569654edd.65.1523540591439; Thu, 12 Apr 2018 06:43:11 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1523540591; cv=none; d=google.com; s=arc-20160816; b=RfAB67i83g5bFfuxvvaVkv7vbVzHQJ2mwPD9y5H7+OwPQKQ7m8w8LJBtflNzG0Nv8p JBuad9i0jEmDOzQHF/n+ssrP+g/T/ZGc8Fx9iQKgigsUdWVotRKwPX41LLlVKkTJBFSi C4dWd56WbXylpvSzZzCENgivKlS5YQ4r30QyrxDNIX3hCYFFAf3m3uDW4OS3oUWmGXKP 5jVwSRxA7LI1ZHYd0DrlBeUGkht5S6umTROYxXad88jfQ4AEZcuGKzaLhUSsZ/4/u7e1 CcHEJMvVzgnxIlklt91xr4VlYDFnWZTKk7750s0nAt/yXCywXmc8efaLMTtRrItuAcFk DrrQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:references:in-reply-to:message-id:date :to:from:arc-authentication-results; bh=IjXUPQdUKLobCKJbMqxa6iKsyIPuJiw0QTclAs1Isi8=; b=AxasGENHsVKVid79qoVMJoNNvtmNYNTL/6a4ywsknx6SqzGMrnSI/BsPu1XWV1WIJi Lrdc/1RBggRTxB4hzwE660LsDn581Z3usKF7U2MlbekJTQAhQnMXv8JJ+G7ztPZ1HCPe EgcZ22Co82PhAT4z7HsETuGsysS2xD4PNLA+kivVzp1oKwVpXh9fGFardyogL/E5MEeA U5T5+FAm6YwHRSNwTBuOcN0WbVLc4fyKs05EqZjMKpJSj5YvnVncSZmPheJFniUQVg+q xQmJnT+awHDrDMVIoXajwhkpv/cDEZU8Pl07ioh3a4XJkazVcPFVYKOzbKjsOwHftGx8 PvVQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Return-Path: Received: from lists.denx.de (dione.denx.de. [81.169.180.215]) by mx.google.com with ESMTP id y9si691538edh.277.2018.04.12.06.43.11; Thu, 12 Apr 2018 06:43:11 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by lists.denx.de (Postfix, from userid 105) id F1A05C21C6A; Thu, 12 Apr 2018 13:42:26 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=none autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id B9498C21DA2; Thu, 12 Apr 2018 13:42:03 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 7FB4FC21C2C; Thu, 12 Apr 2018 13:42:01 +0000 (UTC) Received: from mx2.suse.de (mx2.suse.de [195.135.220.15]) by lists.denx.de (Postfix) with ESMTPS id F3A49C21C2F for ; Thu, 12 Apr 2018 13:42:00 +0000 (UTC) X-Virus-Scanned: by amavisd-new at test-mx.suse.de Received: from relay2.suse.de (charybdis-ext.suse.de [195.135.220.254]) by mx2.suse.de (Postfix) with ESMTP id 2AA4FAD16; Thu, 12 Apr 2018 13:42:00 +0000 (UTC) From: Alexander Graf To: u-boot@lists.denx.de Date: Thu, 12 Apr 2018 15:41:56 +0200 Message-Id: <20180412134158.69300-2-agraf@suse.de> X-Mailer: git-send-email 2.12.3 In-Reply-To: <20180412134158.69300-1-agraf@suse.de> References: <20180412134158.69300-1-agraf@suse.de> Subject: [U-Boot] [PATCH v2 1/3] tools: zynqmpimage: Add partition read support X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" The zynqmp image format has support for inline partitions which are used by FSBL to describe payloads that are loaded by FSBL itself. While we can't create images that contain partitions (yet), we should still at least be able to examine them and show the user what's inside when we analyze an image created by bootgen. Signed-off-by: Alexander Graf --- v1 -> v2: - prettify defines - fix offset and size outputs - add u-boot as payload target - align CPU names with bif - add shift constants - add U-Boot as potential partition owner - mention documentation source - add HEADER_CPU_SELECT_A53_64BIT define --- tools/zynqmpimage.c | 174 +++++++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 172 insertions(+), 2 deletions(-) diff --git a/tools/zynqmpimage.c b/tools/zynqmpimage.c index a61fb17c40..8117913da3 100644 --- a/tools/zynqmpimage.c +++ b/tools/zynqmpimage.c @@ -7,6 +7,7 @@ * The following Boot Header format/structures and values are defined in the * following documents: * * ug1085 ZynqMP TRM doc v1.4 (Chapter 11, Table 11-4) + * * ug1137 ZynqMP Software Developer Guide v6.0 (Chapter 16) * * Expected Header Size = 0x9C0 * Forced as 'little' endian, 32-bit words @@ -63,6 +64,7 @@ #define HEADER_REGINIT_NULL (cpu_to_le32(0xffffffff)) #define HEADER_WIDTHDETECTION (cpu_to_le32(0xaa995566)) #define HEADER_IMAGEIDENTIFIER (cpu_to_le32(0x584c4e58)) +#define HEADER_CPU_SELECT_A53_64BIT (0x2 << 10) enum { ENCRYPTION_EFUSE = 0xa5c3c5a3, @@ -80,6 +82,78 @@ struct zynqmp_reginit { #define HEADER_INTERRUPT_VECTORS 8 #define HEADER_REGINITS 256 +struct image_header_table { + uint32_t version; /* 0x00 */ + uint32_t nr_parts; /* 0x04 */ + uint32_t partition_header_offset; /* 0x08, divided by 4 */ + uint32_t image_header_offset; /* 0x0c, divided by 4 */ + uint32_t auth_certificate_offset; /* 0x10 */ + uint32_t boot_device; /* 0x14 */ + uint32_t __reserved1[9]; /* 0x18 - 0x38 */ + uint32_t checksum; /* 0x3c */ +}; + +#define PART_ATTR_VEC_LOCATION 0x800000 +#define PART_ATTR_BS_BLOCK_SIZE_MASK 0x700000 +#define PART_ATTR_BS_BLOCK_SIZE_DEFAULT 0x000000 +#define PART_ATTR_BS_BLOCK_SIZE_8MB 0x400000 +#define PART_ATTR_BIG_ENDIAN 0x040000 +#define PART_ATTR_PART_OWNER_MASK 0x030000 +#define PART_ATTR_PART_OWNER_FSBL 0x000000 +#define PART_ATTR_PART_OWNER_UBOOT 0x010000 +#define PART_ATTR_RSA_SIG 0x008000 +#define PART_ATTR_CHECKSUM_MASK 0x007000 +#define PART_ATTR_CHECKSUM_NONE 0x000000 +#define PART_ATTR_CHECKSUM_MD5 0x001000 +#define PART_ATTR_CHECKSUM_SHA2 0x002000 +#define PART_ATTR_CHECKSUM_SHA3 0x003000 +#define PART_ATTR_DEST_CPU_SHIFT 8 +#define PART_ATTR_DEST_CPU_MASK 0x000f00 +#define PART_ATTR_DEST_CPU_NONE 0x000000 +#define PART_ATTR_DEST_CPU_A53_0 0x000100 +#define PART_ATTR_DEST_CPU_A53_1 0x000200 +#define PART_ATTR_DEST_CPU_A53_2 0x000300 +#define PART_ATTR_DEST_CPU_A53_3 0x000400 +#define PART_ATTR_DEST_CPU_R5_0 0x000500 +#define PART_ATTR_DEST_CPU_R5_1 0x000600 +#define PART_ATTR_DEST_CPU_R5_L 0x000700 +#define PART_ATTR_DEST_CPU_PMU 0x000800 +#define PART_ATTR_ENCRYPTED 0x000080 +#define PART_ATTR_DEST_DEVICE_SHIFT 4 +#define PART_ATTR_DEST_DEVICE_MASK 0x000070 +#define PART_ATTR_DEST_DEVICE_NONE 0x000000 +#define PART_ATTR_DEST_DEVICE_PS 0x000010 +#define PART_ATTR_DEST_DEVICE_PL 0x000020 +#define PART_ATTR_DEST_DEVICE_PMU 0x000030 +#define PART_ATTR_DEST_DEVICE_XIP 0x000040 +#define PART_ATTR_A53_EXEC_AARCH32 0x000008 +#define PART_ATTR_TARGET_EL_SHIFT 1 +#define PART_ATTR_TARGET_EL_MASK 0x000006 +#define PART_ATTR_TZ_SECURE 0x000001 + +static const char *dest_cpus[0x10] = { + "none", "a5x-0", "a5x-1", "a5x-2", "a5x-3", "r5-0", "r5-1", + "r5-lockstep", "pmu", "unknown", "unknown", "unknown", "unknown", + "unknown", "unknown", "unknown" +}; + +struct partition_header { + uint32_t len_enc; /* 0x00, divided by 4 */ + uint32_t len_unenc; /* 0x04, divided by 4 */ + uint32_t len; /* 0x08, divided by 4 */ + uint32_t next_partition_offset; /* 0x0c */ + uint64_t entry_point; /* 0x10 */ + uint64_t load_address; /* 0x18 */ + uint32_t offset; /* 0x20, divided by 4 */ + uint32_t attributes; /* 0x24 */ + uint32_t __reserved1; /* 0x28 */ + uint32_t checksum_offset; /* 0x2c, divided by 4 */ + uint32_t __reserved2; /* 0x30 */ + uint32_t auth_certificate_offset; /* 0x34 */ + uint32_t __reserved3; /* 0x38 */ + uint32_t checksum; /* 0x3c */ +}; + struct zynqmp_header { uint32_t interrupt_vectors[HEADER_INTERRUPT_VECTORS]; /* 0x0 */ uint32_t width_detection; /* 0x20 */ @@ -93,7 +167,9 @@ struct zynqmp_header { uint32_t image_stored_size; /* 0x40 */ uint32_t image_attributes; /* 0x44 */ uint32_t checksum; /* 0x48 */ - uint32_t __reserved1[27]; /* 0x4c */ + uint32_t __reserved1[19]; /* 0x4c */ + uint32_t image_header_table_offset; /* 0x98 */ + uint32_t __reserved2[7]; /* 0x9c */ struct zynqmp_reginit register_init[HEADER_REGINITS]; /* 0xb8 */ uint32_t __reserved4[66]; /* 0x9c0 */ }; @@ -132,7 +208,7 @@ static void zynqmpimage_default_header(struct zynqmp_header *ptr) return; ptr->width_detection = HEADER_WIDTHDETECTION; - ptr->image_attributes = 0x800; + ptr->image_attributes = HEADER_CPU_SELECT_A53_64BIT; ptr->image_identifier = HEADER_IMAGEIDENTIFIER; ptr->encryption = cpu_to_le32(ENCRYPTION_NONE); @@ -173,6 +249,81 @@ static int zynqmpimage_verify_header(unsigned char *ptr, int image_size, return 0; } +static void print_partition(const void *ptr, const struct partition_header *ph) +{ + uint32_t attr = le32_to_cpu(ph->attributes); + unsigned long len = le32_to_cpu(ph->len) * 4; + const char *part_owner; + const char *dest_devs[0x8] = { + "none", "PS", "PL", "PMU", "unknown", "unknown", "unknown", + "unknown" + }; + + switch (attr & PART_ATTR_PART_OWNER_MASK) { + case PART_ATTR_PART_OWNER_FSBL: + part_owner = "FSBL"; + break; + case PART_ATTR_PART_OWNER_UBOOT: + part_owner = "U-Boot"; + break; + default: + part_owner = "Unknown"; + break; + } + + printf("%s payload on CPU %s (%s):\n", + part_owner, + dest_cpus[(attr & PART_ATTR_DEST_CPU_MASK) >> 8], + dest_devs[(attr & PART_ATTR_DEST_DEVICE_MASK) >> 4]); + + printf(" Offset : 0x%08x\n", le32_to_cpu(ph->offset) * 4); + printf(" Size : %lu (0x%lx) bytes\n", len, len); + printf(" Load : 0x%08llx", + (unsigned long long)le64_to_cpu(ph->load_address)); + if (ph->load_address != ph->entry_point) + printf(" (entry=0x%08llx)\n", + (unsigned long long)le64_to_cpu(ph->entry_point)); + else + printf("\n"); + printf(" Attributes : "); + + if (attr & PART_ATTR_VEC_LOCATION) + printf("vec "); + + if (attr & PART_ATTR_ENCRYPTED) + printf("encrypted "); + + switch (attr & PART_ATTR_CHECKSUM_MASK) { + case PART_ATTR_CHECKSUM_MD5: + printf("md5 "); + break; + case PART_ATTR_CHECKSUM_SHA2: + printf("sha2 "); + break; + case PART_ATTR_CHECKSUM_SHA3: + printf("sha3 "); + break; + } + + if (attr & PART_ATTR_BIG_ENDIAN) + printf("BigEndian "); + + if (attr & PART_ATTR_RSA_SIG) + printf("RSA "); + + if (attr & PART_ATTR_A53_EXEC_AARCH32) + printf("AArch32 "); + + if (attr & PART_ATTR_TARGET_EL_MASK) + printf("EL%d ", (attr & PART_ATTR_TARGET_EL_MASK) >> 1); + + if (attr & PART_ATTR_TZ_SECURE) + printf("secure "); + printf("\n"); + + printf(" Checksum : 0x%08x\n", le32_to_cpu(ph->checksum)); +} + static void zynqmpimage_print_header(const void *ptr) { struct zynqmp_header *zynqhdr = (struct zynqmp_header *)ptr; @@ -213,6 +364,25 @@ static void zynqmpimage_print_header(const void *ptr) le32_to_cpu(zynqhdr->register_init[i].data)); } + if (zynqhdr->image_header_table_offset) { + struct image_header_table *iht = (void*)ptr + + zynqhdr->image_header_table_offset; + struct partition_header *ph; + uint32_t ph_offset; + int i; + + ph_offset = le32_to_cpu(iht->partition_header_offset) * 4; + ph = (void*)ptr + ph_offset; + for (i = 0; i < le32_to_cpu(iht->nr_parts); i++) { + uint32_t next = le32_to_cpu(ph->next_partition_offset) * 4; + + /* Partition 0 is the base image itself */ + if (i) + print_partition(ptr, ph); + ph = (void*)ptr + next; + } + } + free(dynamic_header); }