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[81.169.180.215]) by mx.google.com with ESMTP id 4si6153213ede.540.2017.12.18.01.42.37; Mon, 18 Dec 2017 01:42:37 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=J8T2mJ1K; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: by lists.denx.de (Postfix, from userid 105) id 90C70C21F18; Mon, 18 Dec 2017 09:37:28 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 97D36C21E55; Mon, 18 Dec 2017 09:36:19 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 7DF08C21E13; Mon, 18 Dec 2017 09:35:42 +0000 (UTC) Received: from fllnx209.ext.ti.com (fllnx209.ext.ti.com [198.47.19.16]) by lists.denx.de (Postfix) with ESMTPS id 3FC82C21E67 for ; Mon, 18 Dec 2017 09:35:38 +0000 (UTC) Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by fllnx209.ext.ti.com (8.15.1/8.15.1) with ESMTP id vBI9ZAQ0014445; Mon, 18 Dec 2017 03:35:10 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1513589710; bh=uQVVx1IIPlRRuQ9UPl9XXrMcwzdv6sHFD+M351B0/tE=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=J8T2mJ1Kb7xecpw9rB771yiEjxTJqmPkpMth8/pZZ/5WGoUnuxVty3aCbwHyIc3tL ZgFprRCYPBjqhTVweK/Kqjm47iY+Z6dOkpPI5uepl0HYa72YTWC5Xg/O3Ztur/zwA7 qooz7HZcsFBqXyBLBAoEO5vg4v6X3txwPDgdJn00= Received: from DFLE101.ent.ti.com (dfle101.ent.ti.com [10.64.6.22]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id vBI9Z5bx004814; Mon, 18 Dec 2017 03:35:05 -0600 Received: from DFLE109.ent.ti.com (10.64.6.30) by DFLE101.ent.ti.com (10.64.6.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1261.35; Mon, 18 Dec 2017 03:35:04 -0600 Received: from dlep32.itg.ti.com (157.170.170.100) by DFLE109.ent.ti.com (10.64.6.30) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1261.35 via Frontend Transport; Mon, 18 Dec 2017 03:35:05 -0600 Received: from uda0131933.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id vBI9Z1QU028762; Mon, 18 Dec 2017 03:35:03 -0600 From: Lokesh Vutla To: Tom Rini , Date: Mon, 18 Dec 2017 15:04:13 +0530 Message-ID: <20171218093425.12235-2-lokeshvutla@ti.com> X-Mailer: git-send-email 2.15.1 In-Reply-To: <20171218093425.12235-1-lokeshvutla@ti.com> References: <20171218093425.12235-1-lokeshvutla@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Cc: Tero Kristo Subject: [U-Boot] [PATCH 01/13] drivers: dma: ti-edma3: add support for memory fill X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Tero Kristo Add support for simple memory fill operation. With large data sizes it is much faster to use EDMA for memory fill rather than CPU. Signed-off-by: Tero Kristo Signed-off-by: Lokesh Vutla --- arch/arm/include/asm/ti-common/ti-edma3.h | 2 ++ drivers/dma/ti-edma3.c | 55 +++++++++++++++++++++++++++---- 2 files changed, 50 insertions(+), 7 deletions(-) diff --git a/arch/arm/include/asm/ti-common/ti-edma3.h b/arch/arm/include/asm/ti-common/ti-edma3.h index 6a7a321c1b..3f41d34a7a 100644 --- a/arch/arm/include/asm/ti-common/ti-edma3.h +++ b/arch/arm/include/asm/ti-common/ti-edma3.h @@ -119,5 +119,7 @@ void edma3_set_transfer_params(u32 base, int slot, int acnt, enum edma3_sync_dimension sync_mode); void edma3_transfer(unsigned long edma3_base_addr, unsigned int edma_slot_num, void *dst, void *src, size_t len); +void edma3_fill(unsigned long edma3_base_addr, unsigned int edma_slot_num, + void *dst, u8 val, size_t len); #endif diff --git a/drivers/dma/ti-edma3.c b/drivers/dma/ti-edma3.c index 635eb7876d..852c9e1fd7 100644 --- a/drivers/dma/ti-edma3.c +++ b/drivers/dma/ti-edma3.c @@ -34,10 +34,14 @@ #define EDMA3_QEESR 0x108c #define EDMA3_QSECR 0x1094 +#define EDMA_FILL_BUFFER_SIZE 512 + struct ti_edma3_priv { u32 base; }; +static u8 edma_fill_buffer[EDMA_FILL_BUFFER_SIZE] __aligned(ARCH_DMA_MINALIGN); + /** * qedma3_start - start qdma on a channel * @base: base address of edma @@ -391,7 +395,7 @@ void qedma3_stop(u32 base, struct edma3_channel_config *cfg) } void __edma3_transfer(unsigned long edma3_base_addr, unsigned int edma_slot_num, - void *dst, void *src, size_t len) + void *dst, void *src, size_t len, size_t s_len) { struct edma3_slot_config slot; struct edma3_channel_config edma_channel; @@ -401,7 +405,11 @@ void __edma3_transfer(unsigned long edma3_base_addr, unsigned int edma_slot_num, unsigned int addr = (unsigned int) (dst); unsigned int max_acnt = 0x7FFFU; - if (len > max_acnt) { + if (len > s_len) { + b_cnt_value = (len / s_len); + rem_bytes = (len % s_len); + a_cnt_value = s_len; + } else if (len > max_acnt) { b_cnt_value = (len / max_acnt); rem_bytes = (len % max_acnt); a_cnt_value = max_acnt; @@ -412,7 +420,10 @@ void __edma3_transfer(unsigned long edma3_base_addr, unsigned int edma_slot_num, slot.acnt = a_cnt_value; slot.bcnt = b_cnt_value; slot.ccnt = 1; - slot.src_bidx = a_cnt_value; + if (len == s_len) + slot.src_bidx = a_cnt_value; + else + slot.src_bidx = 0; slot.dst_bidx = a_cnt_value; slot.src_cidx = 0; slot.dst_cidx = 0; @@ -438,8 +449,11 @@ void __edma3_transfer(unsigned long edma3_base_addr, unsigned int edma_slot_num, if (rem_bytes != 0) { slot.opt = 0; - slot.src = - (b_cnt_value * max_acnt) + ((unsigned int) src); + if (len == s_len) + slot.src = + (b_cnt_value * max_acnt) + ((unsigned int) src); + else + slot.src = (unsigned int) src; slot.acnt = rem_bytes; slot.bcnt = 1; slot.ccnt = 1; @@ -468,12 +482,39 @@ void __edma3_transfer(unsigned long edma3_base_addr, unsigned int edma_slot_num, } } +void __edma3_fill(unsigned long edma3_base_addr, unsigned int edma_slot_num, + void *dst, u8 val, size_t len) +{ + int xfer_len; + int max_xfer = EDMA_FILL_BUFFER_SIZE * 65535; + + memset((void *)edma_fill_buffer, val, sizeof(edma_fill_buffer)); + + while (len) { + xfer_len = len; + if (xfer_len > max_xfer) + xfer_len = max_xfer; + + __edma3_transfer(edma3_base_addr, edma_slot_num, dst, + edma_fill_buffer, xfer_len, + EDMA_FILL_BUFFER_SIZE); + len -= xfer_len; + dst += xfer_len; + } +} + #ifndef CONFIG_DMA void edma3_transfer(unsigned long edma3_base_addr, unsigned int edma_slot_num, void *dst, void *src, size_t len) { - __edma3_transfer(edma3_base_addr, edma_slot_num, dst, src, len); + __edma3_transfer(edma3_base_addr, edma_slot_num, dst, src, len, len); +} + +void edma3_fill(unsigned long edma3_base_addr, unsigned int edma_slot_num, + void *dst, u8 val, size_t len) +{ + __edma3_fill(edma3_base_addr, edma_slot_num, dst, val, len); } #else @@ -488,7 +529,7 @@ static int ti_edma3_transfer(struct udevice *dev, int direction, void *dst, switch (direction) { case DMA_MEM_TO_MEM: - __edma3_transfer(priv->base, 1, dst, src, len); + __edma3_transfer(priv->base, 1, dst, src, len, len); break; default: pr_err("Transfer type not implemented in DMA driver\n");