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[81.169.180.215]) by mx.google.com with ESMTP id b50si3070630edc.312.2017.09.08.12.10.20; Fri, 08 Sep 2017 12:10:20 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=lR1MZf5O; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: by lists.denx.de (Postfix, from userid 105) id 76DE3C21CA5; Fri, 8 Sep 2017 19:10:18 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.8 required=5.0 tests=RCVD_IN_DNSWL_NONE, T_DKIM_INVALID, UPPERCASE_50_75 autolearn=no autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 5F234C21E84; Fri, 8 Sep 2017 19:10:14 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 5B54EC21DC8; Fri, 8 Sep 2017 19:10:01 +0000 (UTC) Received: from lelnx194.ext.ti.com (lelnx194.ext.ti.com [198.47.27.80]) by lists.denx.de (Postfix) with ESMTPS id D4F21C21F0E for ; Fri, 8 Sep 2017 19:09:57 +0000 (UTC) Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by lelnx194.ext.ti.com (8.15.1/8.15.1) with ESMTP id v88J8aaR009863; Fri, 8 Sep 2017 14:08:36 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1504897716; bh=XJZzJXEA/umRuhp/elhW0ZXFmlQGsL4PgVJFdqu0+Ec=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=lR1MZf5ODIAm5VTBkdPF9VMQG9sxBjrOnaHMBR6VI9PvYJkd5xOzQaWLdrw+KJUpq 0zdVtzF2T2VTF8n8QsmGBehXVHzcVyS/lcMDretre5455Mqztl0ddKjToIe366NtgN 1M/TYPfFv0uf51vGQeRNz3Fj6UiLeJBO7XcfvGi4= Received: from DLEE113.ent.ti.com (dlee113.ent.ti.com [157.170.170.24]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id v88J8ax3023193; Fri, 8 Sep 2017 14:08:36 -0500 Received: from DLEE105.ent.ti.com (157.170.170.35) by DLEE113.ent.ti.com (157.170.170.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.1.845.34; Fri, 8 Sep 2017 14:08:36 -0500 Received: from dflp32.itg.ti.com (10.64.6.15) by DLEE105.ent.ti.com (157.170.170.35) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.845.34 via Frontend Transport; Fri, 8 Sep 2017 14:08:36 -0500 Received: from legion.dal.design.ti.com (legion.dal.design.ti.com [128.247.22.53]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id v88J8ac6021719; Fri, 8 Sep 2017 14:08:36 -0500 Received: from localhost (irmo.dhcp.ti.com [128.247.58.153]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id v88J8a302538; Fri, 8 Sep 2017 14:08:36 -0500 (CDT) From: Suman Anna To: Uri Mashiach Date: Fri, 8 Sep 2017 14:08:24 -0500 Message-ID: <20170908190825.21515-2-s-anna@ti.com> X-Mailer: git-send-email 2.13.1 In-Reply-To: <20170908190825.21515-1-s-anna@ti.com> References: <20170908190825.21515-1-s-anna@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Cc: Tom Rini , u-boot@lists.denx.de Subject: [U-Boot] [PATCH 1/2] arm: am57xx: cl-som-am57x: Use new pinctrl macros X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Commit 6ae4c3efbd62 ("ARM: DRA7: Add pinctrl register definitions") has added new macros for pinmux configuration in line with the kernel definitions. Fixup the current pinctrl data for the CompuLab CL-SOM-AM57x board to use these new macros to facilitate the removal of the old macros. NOTE: The PEN and PDIS macro values used previously were actually defined inversely, a value of 1 in bit position 16 actually means that the internal pullup/pulldown is disabled and not enabled as inferred by PEN. So, previous pinmux config data such as (PDIS | PTU) is confusing as it actually was meant for enabling internal pullup. The data is fixed up only to be equivalent to the previous data. Signed-off-by: Suman Anna --- board/compulab/cl-som-am57x/mux.c | 105 +++++++++++++++++++------------------- 1 file changed, 53 insertions(+), 52 deletions(-) diff --git a/board/compulab/cl-som-am57x/mux.c b/board/compulab/cl-som-am57x/mux.c index 0db0609727f7..21449ca029b0 100644 --- a/board/compulab/cl-som-am57x/mux.c +++ b/board/compulab/cl-som-am57x/mux.c @@ -12,97 +12,98 @@ /* Serial console */ static const struct pad_conf_entry cl_som_am57x_padconf_console[] = { - {UART3_RXD, (FSC | IEN | PDIS | PTU | M0)}, /* UART3_RXD */ - {UART3_TXD, (FSC | IEN | PDIS | PTU | M0)}, /* UART3_TXD */ + {UART3_RXD, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* UART3_RXD */ + {UART3_TXD, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* UART3_TXD */ }; /* PMIC I2C */ static const struct pad_conf_entry cl_som_am57x_padconf_pmic[] = { - {MCASP1_ACLKR, (IEN | PEN | M10)}, /* MCASP1_ACLKR.I2C4_SDA */ - {MCASP1_FSR, (IEN | PEN | M10)}, /* MCASP1_FSR.I2C4_SCL */ + {MCASP1_ACLKR, (M10 | PIN_INPUT)}, /* MCASP1_ACLKR.I2C4_SDA */ + {MCASP1_FSR, (M10 | PIN_INPUT)}, /* MCASP1_FSR.I2C4_SCL */ }; /* Green GPIO led */ static const struct pad_conf_entry cl_som_am57x_padconf_green_led[] = { - {GPMC_A15, (IDIS | PDIS | PTD | M14)}, /* GPMC_A15.GPIO2_5 */ + {GPMC_A15, (M14 | PIN_OUTPUT_PULLDOWN)}, /* GPMC_A15.GPIO2_5 */ }; /* MMC/SD Card */ static const struct pad_conf_entry cl_som_am57x_padconf_sd_card[] = { - {MMC1_CLK, (IEN | PDIS | PTU | M0) }, /* MMC1_CLK */ - {MMC1_CMD, (IEN | PDIS | PTU | M0) }, /* MMC1_CMD */ - {MMC1_DAT0, (IEN | PDIS | PTU | M0) }, /* MMC1_DAT0 */ - {MMC1_DAT1, (IEN | PDIS | PTU | M0) }, /* MMC1_DAT1 */ - {MMC1_DAT2, (IEN | PDIS | PTU | M0) }, /* MMC1_DAT2 */ - {MMC1_DAT3, (IEN | PDIS | PTU | M0) }, /* MMC1_DAT3 */ - {MMC1_SDCD, (IEN | PEN | M14)}, /* MMC1_SDCD */ - {MMC1_SDWP, (IEN | PEN | M14)}, /* MMC1_SDWP */ + {MMC1_CLK, (M0 | PIN_INPUT_PULLUP)}, /* MMC1_CLK */ + {MMC1_CMD, (M0 | PIN_INPUT_PULLUP)}, /* MMC1_CMD */ + {MMC1_DAT0, (M0 | PIN_INPUT_PULLUP)}, /* MMC1_DAT0 */ + {MMC1_DAT1, (M0 | PIN_INPUT_PULLUP)}, /* MMC1_DAT1 */ + {MMC1_DAT2, (M0 | PIN_INPUT_PULLUP)}, /* MMC1_DAT2 */ + {MMC1_DAT3, (M0 | PIN_INPUT_PULLUP)}, /* MMC1_DAT3 */ + {MMC1_SDCD, (M14 | PIN_INPUT) }, /* MMC1_SDCD */ + {MMC1_SDWP, (M14 | PIN_INPUT) }, /* MMC1_SDWP */ }; /* WiFi - must be in the safe mode on boot */ static const struct pad_conf_entry cl_som_am57x_padconf_wifi[] = { - {UART1_CTSN, (IEN | M15)}, /* UART1_CTSN */ - {UART1_RTSN, (IEN | M15)}, /* UART1_RTSN */ - {UART2_RXD, (IEN | M15)}, /* UART2_RXD */ - {UART2_TXD, (IEN | M15)}, /* UART2_TXD */ - {UART2_CTSN, (IEN | M15)}, /* UART2_CTSN */ - {UART2_RTSN, (IEN | M15)}, /* UART2_RTSN */ + {UART1_CTSN, (M15 | PIN_INPUT_PULLDOWN)}, /* UART1_CTSN */ + {UART1_RTSN, (M15 | PIN_INPUT_PULLDOWN)}, /* UART1_RTSN */ + {UART2_RXD, (M15 | PIN_INPUT_PULLDOWN)}, /* UART2_RXD */ + {UART2_TXD, (M15 | PIN_INPUT_PULLDOWN)}, /* UART2_TXD */ + {UART2_CTSN, (M15 | PIN_INPUT_PULLDOWN)}, /* UART2_CTSN */ + {UART2_RTSN, (M15 | PIN_INPUT_PULLDOWN)}, /* UART2_RTSN */ }; /* QSPI */ static const struct pad_conf_entry cl_som_am57x_padconf_qspi[] = { - {GPMC_A13, (IEN | PEN | M1)}, /* GPMC_A13.QSPI1_RTCLK */ - {GPMC_A18, (IEN | PEN | M1)}, /* GPMC_A18.QSPI1_SCLK */ - {GPMC_A16, (IEN | PEN | M1)}, /* GPMC_A16.QSPI1_D0 */ - {GPMC_A17, (IEN | PEN | M1)}, /* GPMC_A17.QSPI1_D1 */ - {GPMC_CS2, (IEN | PDIS | PTU | M1)}, /* GPMC_CS2.QSPI1_CS0 */ + {GPMC_A13, (M1 | PIN_INPUT) }, /* GPMC_A13.QSPI1_RTCLK */ + {GPMC_A18, (M1 | PIN_INPUT) }, /* GPMC_A18.QSPI1_SCLK */ + {GPMC_A16, (M1 | PIN_INPUT) }, /* GPMC_A16.QSPI1_D0 */ + {GPMC_A17, (M1 | PIN_INPUT) }, /* GPMC_A17.QSPI1_D1 */ + {GPMC_CS2, (M1 | PIN_INPUT_PULLUP)}, /* GPMC_CS2.QSPI1_CS0 */ }; /* GPIO Expander I2C */ static const struct pad_conf_entry cl_som_am57x_padconf_i2c_gpio[] = { - {MCASP1_AXR0, (IEN | PEN | M10)}, /* MCASP1_AXR0.I2C5_SDA */ - {MCASP1_AXR1, (IEN | PEN | M10)}, /* MCASP1_AXR1.I2C5_SCL */ + {MCASP1_AXR0, (M10 | PIN_INPUT)}, /* MCASP1_AXR0.I2C5_SDA */ + {MCASP1_AXR1, (M10 | PIN_INPUT)}, /* MCASP1_AXR1.I2C5_SCL */ }; /* eMMC internal storage */ static const struct pad_conf_entry cl_som_am57x_padconf_emmc[] = { - {GPMC_A19, (IEN | PDIS | PTU | M1)}, /* GPMC_A19.MMC2_DAT4 */ - {GPMC_A20, (IEN | PDIS | PTU | M1)}, /* GPMC_A20.MMC2_DAT5 */ - {GPMC_A21, (IEN | PDIS | PTU | M1)}, /* GPMC_A21.MMC2_DAT6 */ - {GPMC_A22, (IEN | PDIS | PTU | M1)}, /* GPMC_A22.MMC2_DAT7 */ - {GPMC_A23, (IEN | PDIS | PTU | M1)}, /* GPMC_A23.MMC2_CLK */ - {GPMC_A24, (IEN | PDIS | PTU | M1)}, /* GPMC_A24.MMC2_DAT0 */ - {GPMC_A25, (IEN | PDIS | PTU | M1)}, /* GPMC_A25.MMC2_DAT1 */ - {GPMC_A26, (IEN | PDIS | PTU | M1)}, /* GPMC_A26.MMC2_DAT2 */ - {GPMC_A27, (IEN | PDIS | PTU | M1)}, /* GPMC_A27.MMC2_DAT3 */ - {GPMC_CS1, (IEN | PDIS | PTU | M1)}, /* GPMC_CS1.MMC2_CMD */ + {GPMC_A19, (M1 | PIN_INPUT_PULLUP)}, /* GPMC_A19.MMC2_DAT4 */ + {GPMC_A20, (M1 | PIN_INPUT_PULLUP)}, /* GPMC_A20.MMC2_DAT5 */ + {GPMC_A21, (M1 | PIN_INPUT_PULLUP)}, /* GPMC_A21.MMC2_DAT6 */ + {GPMC_A22, (M1 | PIN_INPUT_PULLUP)}, /* GPMC_A22.MMC2_DAT7 */ + {GPMC_A23, (M1 | PIN_INPUT_PULLUP)}, /* GPMC_A23.MMC2_CLK */ + {GPMC_A24, (M1 | PIN_INPUT_PULLUP)}, /* GPMC_A24.MMC2_DAT0 */ + {GPMC_A25, (M1 | PIN_INPUT_PULLUP)}, /* GPMC_A25.MMC2_DAT1 */ + {GPMC_A26, (M1 | PIN_INPUT_PULLUP)}, /* GPMC_A26.MMC2_DAT2 */ + {GPMC_A27, (M1 | PIN_INPUT_PULLUP)}, /* GPMC_A27.MMC2_DAT3 */ + {GPMC_CS1, (M1 | PIN_INPUT_PULLUP)}, /* GPMC_CS1.MMC2_CMD */ }; /* usb1_drvvbus */ static const struct pad_conf_entry cl_som_am57x_padconf_usb[] = { - {USB1_DRVVBUS, (M0 | FSC) }, /* USB1_DRVVBUS.USB1_DRVVBUS */ + /* USB1_DRVVBUS.USB1_DRVVBUS */ + {USB1_DRVVBUS, (M0 | PIN_OUTPUT_PULLDOWN | SLEWCONTROL) }, }; /* Ethernet */ static const struct pad_conf_entry cl_som_am57x_padconf_ethernet[] = { /* MDIO bus */ - {VIN2A_D10, (PDIS | PTU | M3) }, /* VIN2A_D10.MDIO_MCLK */ - {VIN2A_D11, (IEN | PDIS | PTU | M3) }, /* VIN2A_D11.MDIO_D */ + {VIN2A_D10, (M3 | PIN_OUTPUT_PULLUP) }, /* VIN2A_D10.MDIO_MCLK */ + {VIN2A_D11, (M3 | PIN_INPUT_PULLUP) }, /* VIN2A_D11.MDIO_D */ /* EMAC Slave 1 at addr 0x1 - Default interface */ - {VIN2A_D12, (IDIS | PEN | M3) }, /* VIN2A_D12.RGMII1_TXC */ - {VIN2A_D13, (IDIS | PEN | M3) }, /* VIN2A_D13.RGMII1_TXCTL */ - {VIN2A_D14, (IDIS | PEN | M3) }, /* VIN2A_D14.RGMII1_TXD3 */ - {VIN2A_D15, (IDIS | PEN | M3) }, /* VIN2A_D15.RGMII1_TXD2 */ - {VIN2A_D16, (IDIS | PEN | M3) }, /* VIN2A_D16.RGMII1_TXD1 */ - {VIN2A_D17, (IDIS | PEN | M3) }, /* VIN2A_D17.RGMII1_TXD0 */ - {VIN2A_D18, (IEN | PDIS | PTD | M3) }, /* VIN2A_D18.RGMII1_RXC */ - {VIN2A_D19, (IEN | PDIS | PTD | M3) }, /* VIN2A_D19.RGMII1_RXCTL */ - {VIN2A_D20, (IEN | PDIS | PTD | M3) }, /* VIN2A_D20.RGMII1_RXD3 */ - {VIN2A_D21, (IEN | PDIS | PTD | M3) }, /* VIN2A_D21.RGMII1_RXD2 */ - {VIN2A_D22, (IEN | PDIS | PTD | M3) }, /* VIN2A_D22.RGMII1_RXD1 */ - {VIN2A_D23, (IEN | PDIS | PTD | M3) }, /* VIN2A_D23.RGMII1_RXD0 */ + {VIN2A_D12, (M3 | PIN_OUTPUT) }, /* VIN2A_D12.RGMII1_TXC */ + {VIN2A_D13, (M3 | PIN_OUTPUT) }, /* VIN2A_D13.RGMII1_TXCTL */ + {VIN2A_D14, (M3 | PIN_OUTPUT) }, /* VIN2A_D14.RGMII1_TXD3 */ + {VIN2A_D15, (M3 | PIN_OUTPUT) }, /* VIN2A_D15.RGMII1_TXD2 */ + {VIN2A_D16, (M3 | PIN_OUTPUT) }, /* VIN2A_D16.RGMII1_TXD1 */ + {VIN2A_D17, (M3 | PIN_OUTPUT) }, /* VIN2A_D17.RGMII1_TXD0 */ + {VIN2A_D18, (M3 | PIN_INPUT_PULLDOWN) }, /* VIN2A_D18.RGMII1_RXC */ + {VIN2A_D19, (M3 | PIN_INPUT_PULLDOWN) }, /* VIN2A_D19.RGMII1_RXCTL */ + {VIN2A_D20, (M3 | PIN_INPUT_PULLDOWN) }, /* VIN2A_D20.RGMII1_RXD3 */ + {VIN2A_D21, (M3 | PIN_INPUT_PULLDOWN) }, /* VIN2A_D21.RGMII1_RXD2 */ + {VIN2A_D22, (M3 | PIN_INPUT_PULLDOWN) }, /* VIN2A_D22.RGMII1_RXD1 */ + {VIN2A_D23, (M3 | PIN_INPUT_PULLDOWN) }, /* VIN2A_D23.RGMII1_RXD0 */ /* Eth PHY1 reset GPIOs*/ - {VIN2A_CLK0, (IDIS | PDIS | PTD | M14)}, /* VIN2A_CLK0.GPIO3_28 */ + {VIN2A_CLK0, (M14 | PIN_OUTPUT_PULLDOWN)}, /* VIN2A_CLK0.GPIO3_28 */ }; #define SET_MUX(mux_array) do_set_mux32((*ctrl)->control_padconf_core_base, \