From patchwork Tue Nov 29 13:23:39 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabien Parent X-Patchwork-Id: 84806 Delivered-To: patch@linaro.org Received: by 10.140.20.101 with SMTP id 92csp1593494qgi; Tue, 29 Nov 2016 05:25:05 -0800 (PST) X-Received: by 10.194.108.10 with SMTP id hg10mr28204291wjb.58.1480425905755; Tue, 29 Nov 2016 05:25:05 -0800 (PST) Return-Path: Received: from theia.denx.de (theia.denx.de. [85.214.87.163]) by mx.google.com with ESMTP id i128si2475315wme.137.2016.11.29.05.25.05; Tue, 29 Nov 2016 05:25:05 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 85.214.87.163 as permitted sender) client-ip=85.214.87.163; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@baylibre-com.20150623.gappssmtp.com; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 85.214.87.163 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id BD26BB38A7; Tue, 29 Nov 2016 14:24:42 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id bUsc-LeX9mn6; Tue, 29 Nov 2016 14:24:42 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id E6D37B38CB; Tue, 29 Nov 2016 14:24:22 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 3055FB384F for ; Tue, 29 Nov 2016 14:24:02 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id ywxpZU_xxGEx for ; Tue, 29 Nov 2016 14:24:02 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-wm0-f47.google.com (mail-wm0-f47.google.com [74.125.82.47]) by theia.denx.de (Postfix) with ESMTPS id 0AB67A757A for ; Tue, 29 Nov 2016 14:23:57 +0100 (CET) Received: by mail-wm0-f47.google.com with SMTP id g23so237582113wme.1 for ; Tue, 29 Nov 2016 05:23:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=0GXt1oRgr7GEV2RX4yesAio5TLyPShDaV4kwJJkJ7Xk=; b=HkKF9Ly7HsITWUyUgYUYeLCNoXNZek0YX23mDNXKon2KlRr/d9WT1i8hotL6qYpk4z /uLRDbpBnhR9KrNBxhKF2BYzFrUvc1XZ0qo8PJXW9d2Lea8wthxLx6ldnSicQxdg5Zh/ B64ExyYrFu4NsKmCKlu6OUmvyGx3Qb/FkXVWiblsrYY2kr33LxK7ivIkBhmfNLm0yR6t 4YBPF0NrrNdyrKEFzw/iu169CaQDFC2UCg6DwDB+rsTnMAz664/b2tfwf1YDVvtuwd2J M88hatboA28sChTbAZQ3BHDEfvTMdcmIDvpGOxxS2dPHJtjRMw4LMhlYn5dGgqmJUMtF x5Rg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=0GXt1oRgr7GEV2RX4yesAio5TLyPShDaV4kwJJkJ7Xk=; b=XYkfaMDHgUJoJ4xOrmvXORgox4Goy59VVYlj8Leb5NLPU0BmQUq561Mr5EYdPdDmND GJvvOLq+gebuKgG3671DodAt8qszaPKgID1G5FgH/5JT8QBfUzfTPMn/Y3osuFnpR2I7 QHJ9NvE4dhzsKAZkAXlxAyhMPWu2ONQ94K799icI2z390XraNcqEa5J9/BXHGnlPu8r9 E/ASKepIkV/lS1RM/mUHnTMtRdHQDWl2F9qwDBHZI0w6tYd1UGf9fSuFD9kZgkuY/YQ9 V3jZl2XZtmpyLrGgGQh57iLz5cU2Q7gPFNMXMfQUC+aQegR1tFe5bmEhJmnmH3TxW9Wi mPwg== X-Gm-Message-State: AKaTC03nALHGhnMMY422+Y2Ci03OKIk31TD7wGaybHHI4hsibuBEMVdg0mU++tqWBzSuZTLJ X-Received: by 10.28.178.10 with SMTP id b10mr26063805wmf.83.1480425836938; Tue, 29 Nov 2016 05:23:56 -0800 (PST) Received: from localhost.localdomain ([90.63.244.31]) by smtp.gmail.com with ESMTPSA id wg8sm67819337wjb.42.2016.11.29.05.23.56 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 29 Nov 2016 05:23:56 -0800 (PST) From: Fabien Parent To: u-boot@lists.denx.de Date: Tue, 29 Nov 2016 14:23:39 +0100 Message-Id: <20161129132341.18254-5-fparent@baylibre.com> X-Mailer: git-send-email 2.10.2 In-Reply-To: <20161129132341.18254-1-fparent@baylibre.com> References: <20161129132341.18254-1-fparent@baylibre.com> Cc: Tom Rini Subject: [U-Boot] [PATCH v3 4/6] davinci: omapl138_lcdk: configure ddr2 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" The SPL is unable to load u-boot because the DDR2 is not configured. Configure the DDR2. Signed-off-by: Fabien Parent --- v2 -> v3 * Use new Kconfig option SYS_DA850_DDR_INIT instead of defining it in the config header file v1 -> v2 * New patch --- arch/arm/mach-davinci/Kconfig | 1 + include/configs/omapl138_lcdk.h | 41 +++++++++++++++++++++++++++++++++++++++++ 2 files changed, 42 insertions(+) -- 2.10.2 _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot Reviewed-by: Tom Rini diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig index 067b6c3..c593dad 100644 --- a/arch/arm/mach-davinci/Kconfig +++ b/arch/arm/mach-davinci/Kconfig @@ -23,6 +23,7 @@ config TARGET_OMAPL138_LCDK bool "OMAPL138 LCDK" select SUPPORT_SPL select SYS_DA850_PLL_INIT + select SYS_DA850_DDR_INIT config TARGET_CALIMAIN bool "Calimain board" diff --git a/include/configs/omapl138_lcdk.h b/include/configs/omapl138_lcdk.h index 854fc47..9db9cea 100644 --- a/include/configs/omapl138_lcdk.h +++ b/include/configs/omapl138_lcdk.h @@ -79,6 +79,47 @@ #define CONFIG_SYS_DA850_PLL1_PLLM 21 /* + * DDR2 memory configuration + */ +#define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \ + DV_DDR_PHY_EXT_STRBEN | \ + (0x5 << DV_DDR_PHY_RD_LATENCY_SHIFT)) + +#define CONFIG_SYS_DA850_DDR2_SDBCR ( \ + (1 << DV_DDR_SDCR_DDR2EN_SHIFT) | \ + (1 << DV_DDR_SDCR_DDREN_SHIFT) | \ + (1 << DV_DDR_SDCR_SDRAMEN_SHIFT) | \ + (1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) | \ + (4 << DV_DDR_SDCR_CL_SHIFT) | \ + (3 << DV_DDR_SDCR_IBANK_SHIFT) | \ + (2 << DV_DDR_SDCR_PAGESIZE_SHIFT)) + +/* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */ +#define CONFIG_SYS_DA850_DDR2_SDBCR2 0 + +#define CONFIG_SYS_DA850_DDR2_SDTIMR ( \ + (19 << DV_DDR_SDTMR1_RFC_SHIFT) | \ + (1 << DV_DDR_SDTMR1_RP_SHIFT) | \ + (1 << DV_DDR_SDTMR1_RCD_SHIFT) | \ + (2 << DV_DDR_SDTMR1_WR_SHIFT) | \ + (6 << DV_DDR_SDTMR1_RAS_SHIFT) | \ + (8 << DV_DDR_SDTMR1_RC_SHIFT) | \ + (1 << DV_DDR_SDTMR1_RRD_SHIFT) | \ + (1 << DV_DDR_SDTMR1_WTR_SHIFT)) + +#define CONFIG_SYS_DA850_DDR2_SDTIMR2 ( \ + (7 << DV_DDR_SDTMR2_RASMAX_SHIFT) | \ + (2 << DV_DDR_SDTMR2_XP_SHIFT) | \ + (0 << DV_DDR_SDTMR2_ODT_SHIFT) | \ + (10 << DV_DDR_SDTMR2_XSNR_SHIFT) | \ + (199 << DV_DDR_SDTMR2_XSRD_SHIFT) | \ + (1 << DV_DDR_SDTMR2_RTP_SHIFT) | \ + (2 << DV_DDR_SDTMR2_CKE_SHIFT)) + +#define CONFIG_SYS_DA850_DDR2_SDRCR 0x00000492 +#define CONFIG_SYS_DA850_DDR2_PBBPR 0x30 + +/* * Serial Driver info */ #define CONFIG_SYS_NS16550_SERIAL