From patchwork Tue Nov 29 06:37:50 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lokesh Vutla X-Patchwork-Id: 84514 Delivered-To: patch@linaro.org Received: by 10.182.1.168 with SMTP id 8csp2108486obn; Mon, 28 Nov 2016 22:39:09 -0800 (PST) X-Received: by 10.194.111.102 with SMTP id ih6mr21414628wjb.214.1480401549696; Mon, 28 Nov 2016 22:39:09 -0800 (PST) Return-Path: Received: from theia.denx.de (theia.denx.de. [85.214.87.163]) by mx.google.com with ESMTP id g1si1200141wmd.9.2016.11.28.22.39.09; Mon, 28 Nov 2016 22:39:09 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 85.214.87.163 as permitted sender) client-ip=85.214.87.163; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 85.214.87.163 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=NONE dis=NONE) header.from=ti.com Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id A5EF8B3840; Tue, 29 Nov 2016 07:39:08 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id muUybeAzwjJL; Tue, 29 Nov 2016 07:39:08 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id B483EA7607; Tue, 29 Nov 2016 07:39:07 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id A2E73A7607 for ; Tue, 29 Nov 2016 07:39:03 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id piWht33EPCZZ for ; Tue, 29 Nov 2016 07:39:03 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from fllnx209.ext.ti.com (fllnx209.ext.ti.com [198.47.19.16]) by theia.denx.de (Postfix) with ESMTPS id 23851A75BC for ; Tue, 29 Nov 2016 07:38:59 +0100 (CET) Received: from dflxv15.itg.ti.com ([128.247.5.124]) by fllnx209.ext.ti.com (8.15.1/8.15.1) with ESMTP id uAT6cv0b004643; Tue, 29 Nov 2016 00:38:57 -0600 Received: from DLEE71.ent.ti.com (dlee71.ent.ti.com [157.170.170.114]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id uAT6culS001753; Tue, 29 Nov 2016 00:38:57 -0600 Received: from dlep32.itg.ti.com (157.170.170.100) by DLEE71.ent.ti.com (157.170.170.114) with Microsoft SMTP Server id 14.3.294.0; Tue, 29 Nov 2016 00:38:56 -0600 Received: from a0131933.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id uAT6cqwS001247; Tue, 29 Nov 2016 00:38:54 -0600 From: Lokesh Vutla To: Tom Rini , Date: Tue, 29 Nov 2016 12:07:50 +0530 Message-ID: <20161129063750.1979-1-lokeshvutla@ti.com> X-Mailer: git-send-email 2.10.1 MIME-Version: 1.0 Cc: Tero Kristo Subject: [U-Boot] [PATCH] ARM: K2G: DDR3: Fix up priv ID for MPU X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Nishanth Menon For ECC enabled DDR, we use EDMA to reset all memory values to 0. For K2E/L/H/K the priv ID of 8 was indicative of ARM, but that is not the case for K2G, where it is 1. Unfortunately, ddr3 code had hard coded the privID and had missed identification previously. Fix the same, else unforeseen behavior can be expected in our reset of DDR contents to 0 for ECC enablement. Signed-off-by: Nishanth Menon Signed-off-by: Lokesh Vutla --- arch/arm/mach-keystone/ddr3.c | 23 +++++++++++++++++++---- 1 file changed, 19 insertions(+), 4 deletions(-) -- 2.10.1 _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot Reviewed-by: Tom Rini diff --git a/arch/arm/mach-keystone/ddr3.c b/arch/arm/mach-keystone/ddr3.c index 6b92530..ee8e12e 100644 --- a/arch/arm/mach-keystone/ddr3.c +++ b/arch/arm/mach-keystone/ddr3.c @@ -138,7 +138,10 @@ static void ddr3_reset_data(u32 base, u32 ddr3_size) puts("\nClear entire DDR3 memory to enable ECC\n"); /* save the SES MPAX regs */ - msmc_get_ses_mpax(8, 0, mpax); + if (cpu_is_k2g()) + msmc_get_ses_mpax(K2G_MSMC_SEGMENT_ARM, 0, mpax); + else + msmc_get_ses_mpax(K2HKLE_MSMC_SEGMENT_ARM, 0, mpax); /* setup edma slot 1 configuration */ slot.opt = EDMA3_SLOPT_TRANS_COMP_INT_ENB | @@ -169,8 +172,17 @@ static void ddr3_reset_data(u32 base, u32 ddr3_size) for (seg = 0; seg < seg_num; seg += KS2_MSMC_MAP_SEG_NUM) { /* map 2GB 36-bit DDR address to 32-bit DDR address in EMIF access slave interface so that edma driver can access */ - msmc_map_ses_segment(8, 0, base >> KS2_MSMC_SEG_SIZE_SHIFT, - KS2_MSMC_DST_SEG_BASE + seg, MPAX_SEG_2G); + if (cpu_is_k2g()) { + msmc_map_ses_segment(K2G_MSMC_SEGMENT_ARM, 0, + base >> KS2_MSMC_SEG_SIZE_SHIFT, + KS2_MSMC_DST_SEG_BASE + seg, + MPAX_SEG_2G); + } else { + msmc_map_ses_segment(K2HKLE_MSMC_SEGMENT_ARM, 0, + base >> KS2_MSMC_SEG_SIZE_SHIFT, + KS2_MSMC_DST_SEG_BASE + seg, + MPAX_SEG_2G); + } if ((seg_num - seg) > KS2_MSMC_MAP_SEG_NUM) edma_blks = KS2_MSMC_MAP_SEG_NUM << @@ -197,7 +209,10 @@ static void ddr3_reset_data(u32 base, u32 ddr3_size) qedma3_stop(KS2_EDMA0_BASE, &edma_channel); /* restore the SES MPAX regs */ - msmc_set_ses_mpax(8, 0, mpax); + if (cpu_is_k2g()) + msmc_set_ses_mpax(K2G_MSMC_SEGMENT_ARM, 0, mpax); + else + msmc_set_ses_mpax(K2HKLE_MSMC_SEGMENT_ARM, 0, mpax); } static void ddr3_ecc_init_range(u32 base)