From patchwork Wed Nov 23 07:24:41 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lokesh Vutla X-Patchwork-Id: 83552 Delivered-To: patch@linaro.org Received: by 10.140.97.165 with SMTP id m34csp2500796qge; Tue, 22 Nov 2016 23:26:26 -0800 (PST) X-Received: by 10.194.82.163 with SMTP id j3mr2144332wjy.232.1479885986280; Tue, 22 Nov 2016 23:26:26 -0800 (PST) Return-Path: Received: from theia.denx.de (theia.denx.de. [85.214.87.163]) by mx.google.com with ESMTP id pb5si29793521wjb.189.2016.11.22.23.26.25; Tue, 22 Nov 2016 23:26:26 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 85.214.87.163 as permitted sender) client-ip=85.214.87.163; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 85.214.87.163 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=NONE dis=NONE) header.from=ti.com Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 1D2D2A757A; Wed, 23 Nov 2016 08:26:15 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id CsnNVJ70arEH; Wed, 23 Nov 2016 08:26:14 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id CBFB8B3832; Wed, 23 Nov 2016 08:26:05 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id BEFBDA7576 for ; Wed, 23 Nov 2016 08:25:54 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id ZCdix5mgESv1 for ; Wed, 23 Nov 2016 08:25:54 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from lelnx193.ext.ti.com (lelnx193.ext.ti.com [198.47.27.77]) by theia.denx.de (Postfix) with ESMTPS id C7A11A754E for ; Wed, 23 Nov 2016 08:25:52 +0100 (CET) Received: from dflxv15.itg.ti.com ([128.247.5.124]) by lelnx193.ext.ti.com (8.15.1/8.15.1) with ESMTP id uAN7Pp4E000604; Wed, 23 Nov 2016 01:25:51 -0600 Received: from DFLE72.ent.ti.com (dfle72.ent.ti.com [128.247.5.109]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id uAN7Pp4A028660; Wed, 23 Nov 2016 01:25:51 -0600 Received: from dlep33.itg.ti.com (157.170.170.75) by DFLE72.ent.ti.com (128.247.5.109) with Microsoft SMTP Server id 14.3.294.0; Wed, 23 Nov 2016 01:25:50 -0600 Received: from a0131933.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id uAN7PegD013363; Wed, 23 Nov 2016 01:25:48 -0600 From: Lokesh Vutla To: Tom Rini , Date: Wed, 23 Nov 2016 12:54:41 +0530 Message-ID: <20161123072441.32630-4-lokeshvutla@ti.com> X-Mailer: git-send-email 2.10.1 In-Reply-To: <20161123072441.32630-1-lokeshvutla@ti.com> References: <20161123072441.32630-1-lokeshvutla@ti.com> MIME-Version: 1.0 Cc: Tero Kristo , Subhajit Paul Subject: [U-Boot] [PATCH v2 3/3] ARM: DRA7: Fixup DSPEVE, IVA and GPU clock frequencies based on OPP X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Suman Anna This patch adds support to update the device-tree blob to adjust the DSP and IVA DPLL clocks pertinent to the selected OPP choice, with the default being OPP_NOM. The voltage settings are done in u-boot, but the actual clock configuration itself is done in kernel because of the following reasons: 1. SoC definition constraints us to NOT to do dynamic voltage scaling ever after the initial avs0 setting in bootloader - so the voltage must be set in bootloader. 2. The voltage level must be set even if the IP blocks like GPU/DSP are unused. 3. The IVA, GPU and DSP DPLLs are not essential for u-boot functionality, and similar DPLL clock configuration code has been cleaned up in v2014.10 u-boot release. See commit, 02c41535b6a4 ("ARM: OMAP4/5: Remove dead code against CONFIG_SYS_CLOCKS_ENABLE_ALL"). The non-essential DPLLs are configured within the kernel during the clock init step when parsing the device tree and creating the clock devices. This approach meets both the u-boot and kernel needs. Signed-off-by: Suman Anna Signed-off-by: Subhajit Paul Signed-off-by: Lokesh Vutla --- arch/arm/mach-omap2/omap5/fdt.c | 136 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 136 insertions(+) -- 2.10.1 _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot Reviewed-by: Tom Rini diff --git a/arch/arm/mach-omap2/omap5/fdt.c b/arch/arm/mach-omap2/omap5/fdt.c index da8d59b..1cc516c 100644 --- a/arch/arm/mach-omap2/omap5/fdt.c +++ b/arch/arm/mach-omap2/omap5/fdt.c @@ -233,6 +233,141 @@ static void ft_hs_fixups(void *fdt, bd_t *bd) } #endif /* #ifdef CONFIG_TI_SECURE_DEVICE */ +#if defined(CONFIG_TARGET_DRA7XX_EVM) || defined(CONFIG_TARGET_AM57XX_EVM) +#define OPP_DSP_CLK_NUM 3 +#define OPP_IVA_CLK_NUM 2 +#define OPP_GPU_CLK_NUM 2 + +const char *dra7_opp_dsp_clk_names[OPP_DSP_CLK_NUM] = { + "dpll_dsp_ck", + "dpll_dsp_m2_ck", + "dpll_dsp_m3x2_ck", +}; + +const char *dra7_opp_iva_clk_names[OPP_IVA_CLK_NUM] = { + "dpll_iva_ck", + "dpll_iva_m2_ck", +}; + +const char *dra7_opp_gpu_clk_names[OPP_GPU_CLK_NUM] = { + "dpll_gpu_ck", + "dpll_gpu_m2_ck", +}; + +/* DSPEVE voltage domain */ +u32 dra7_opp_dsp_clk_rates[NUM_OPPS][OPP_DSP_CLK_NUM] = { + {}, /*OPP_LOW */ + {600000000, 600000000, 400000000}, /* OPP_NOM */ + {700000000, 700000000, 466666667}, /* OPP_OD */ + {750000000, 750000000, 500000000}, /* OPP_HIGH */ +}; + +/* IVA voltage domain */ +u32 dra7_opp_iva_clk_rates[NUM_OPPS][OPP_IVA_CLK_NUM] = { + {}, /* OPP_LOW */ + {1165000000, 388333334}, /* OPP_NOM */ + {860000000, 430000000}, /* OPP_OD */ + {1064000000, 532000000}, /* OPP_HIGH */ +}; + +/* GPU voltage domain */ +u32 dra7_opp_gpu_clk_rates[NUM_OPPS][OPP_GPU_CLK_NUM] = { + {}, /* OPP_LOW */ + {1277000000, 425666667}, /* OPP_NOM */ + {1000000000, 500000000}, /* OPP_OD */ + {1064000000, 532000000}, /* OPP_HIGH */ +}; + +static int ft_fixup_clocks(void *fdt, const char **names, u32 *rates, int num) +{ + int offs, node_offs, ret, i; + uint32_t phandle; + + offs = fdt_path_offset(fdt, "/ocp/l4@4a000000/cm_core_aon@5000/clocks"); + if (offs < 0) { + debug("Could not find cm_core_aon clocks node path offset : %s\n", + fdt_strerror(offs)); + return offs; + } + + for (i = 0; i < num; i++) { + node_offs = fdt_subnode_offset(fdt, offs, names[i]); + if (node_offs < 0) { + debug("Could not find clock sub-node %s: %s\n", + names[i], fdt_strerror(node_offs)); + return offs; + } + + phandle = fdt_get_phandle(fdt, node_offs); + if (!phandle) { + debug("Could not find phandle for clock %s\n", + names[i]); + return -1; + } + + ret = fdt_setprop_u32(fdt, node_offs, "assigned-clocks", + phandle); + if (ret < 0) { + debug("Could not add assigned-clocks property to clock node %s: %s\n", + names[i], fdt_strerror(ret)); + return ret; + } + + ret = fdt_setprop_u32(fdt, node_offs, "assigned-clock-rates", + rates[i]); + if (ret < 0) { + debug("Could not add assigned-clock-rates property to clock node %s: %s\n", + names[i], fdt_strerror(ret)); + return ret; + } + } + + return 0; +} + +static void ft_opp_clock_fixups(void *fdt, bd_t *bd) +{ + const char **clk_names; + u32 *clk_rates; + int ret; + + if (!is_dra72x() && !is_dra7xx()) + return; + + /* fixup DSP clocks */ + clk_names = dra7_opp_dsp_clk_names; + clk_rates = dra7_opp_dsp_clk_rates[get_voltrail_opp(VOLT_EVE)]; + ret = ft_fixup_clocks(fdt, clk_names, clk_rates, OPP_DSP_CLK_NUM); + if (ret) { + printf("ft_fixup_clocks failed for DSP voltage domain: %s\n", + fdt_strerror(ret)); + return; + } + + /* fixup IVA clocks */ + clk_names = dra7_opp_iva_clk_names; + clk_rates = dra7_opp_iva_clk_rates[get_voltrail_opp(VOLT_IVA)]; + ret = ft_fixup_clocks(fdt, clk_names, clk_rates, OPP_IVA_CLK_NUM); + if (ret) { + printf("ft_fixup_clocks failed for IVA voltage domain: %s\n", + fdt_strerror(ret)); + return; + } + + /* fixup GPU clocks */ + clk_names = dra7_opp_gpu_clk_names; + clk_rates = dra7_opp_gpu_clk_rates[get_voltrail_opp(VOLT_GPU)]; + ret = ft_fixup_clocks(fdt, clk_names, clk_rates, OPP_GPU_CLK_NUM); + if (ret) { + printf("ft_fixup_clocks failed for GPU voltage domain: %s\n", + fdt_strerror(ret)); + return; + } +} +#else +static void ft_opp_clock_fixups(void *fdt, bd_t *bd) { } +#endif /* CONFIG_TARGET_DRA7XX_EVM || CONFIG_TARGET_AM57XX_EVM */ + /* * Place for general cpu/SoC FDT fixups. Board specific * fixups should remain in the board files which is where @@ -241,4 +376,5 @@ static void ft_hs_fixups(void *fdt, bd_t *bd) void ft_cpu_setup(void *fdt, bd_t *bd) { ft_hs_fixups(fdt, bd); + ft_opp_clock_fixups(fdt, bd); }