From patchwork Mon Jul 13 16:59:08 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wasim Khan X-Patchwork-Id: 241425 List-Id: U-Boot discussion From: wasim.khan at nxp.com (Wasim Khan) Date: Mon, 13 Jul 2020 22:29:08 +0530 Subject: [PATCH 05/12] arm: dts: ls2080a: add label to pcie nodes in dts In-Reply-To: <1594659555-12669-1-git-send-email-wasim.khan@nxp.com> References: <1594659555-12669-1-git-send-email-wasim.khan@nxp.com> Message-ID: <1594659555-12669-6-git-send-email-wasim.khan@nxp.com> add label to pcie nodes in dts Signed-off-by: Wasim Khan --- arch/arm/dts/fsl-ls2080a.dtsi | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/arch/arm/dts/fsl-ls2080a.dtsi b/arch/arm/dts/fsl-ls2080a.dtsi index 90a0a3f..fae46c4 100644 --- a/arch/arm/dts/fsl-ls2080a.dtsi +++ b/arch/arm/dts/fsl-ls2080a.dtsi @@ -1,7 +1,8 @@ // SPDX-License-Identifier: GPL-2.0+ OR X11 /* - * Freescale ls2080a SOC common device tree source + * NXP ls2080a SOC common device tree source * + * Copyright 2020 NXP * Copyright 2013-2015 Freescale Semiconductor, Inc. */ @@ -127,7 +128,7 @@ dr_mode = "host"; }; - pcie at 3400000 { + pcie1: pcie at 3400000 { compatible = "fsl,ls-pcie", "snps,dw-pcie"; reg = <0x00 0x03400000 0x0 0x80000 /* dbi registers */ 0x00 0x03480000 0x0 0x80000 /* lut registers */ @@ -142,7 +143,7 @@ 0x82000000 0x0 0x40000000 0x10 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ }; - pcie at 3500000 { + pcie2: pcie at 3500000 { compatible = "fsl,ls-pcie", "snps,dw-pcie"; reg = <0x00 0x03500000 0x0 0x80000 /* dbi registers */ 0x00 0x03580000 0x0 0x80000 /* lut registers */ @@ -157,7 +158,7 @@ 0x82000000 0x0 0x40000000 0x12 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ }; - pcie at 3600000 { + pcie3: pcie at 3600000 { compatible = "fsl,ls-pcie", "snps,dw-pcie"; reg = <0x00 0x03600000 0x0 0x80000 /* dbi registers */ 0x00 0x03680000 0x0 0x80000 /* lut registers */ @@ -172,7 +173,7 @@ 0x82000000 0x0 0x40000000 0x14 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ }; - pcie at 3700000 { + pcie4: pcie at 3700000 { compatible = "fsl,ls-pcie", "snps,dw-pcie"; reg = <0x00 0x03700000 0x0 0x80000 /* dbi registers */ 0x00 0x03780000 0x0 0x80000 /* lut registers */