From patchwork Mon Jul 13 16:59:14 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wasim Khan X-Patchwork-Id: 241431 List-Id: U-Boot discussion From: wasim.khan at nxp.com (Wasim Khan) Date: Mon, 13 Jul 2020 22:29:14 +0530 Subject: [PATCH 11/12] pci: ls_pcie_g4: Add size check for config resource In-Reply-To: <1594659555-12669-1-git-send-email-wasim.khan@nxp.com> References: <1594659555-12669-1-git-send-email-wasim.khan@nxp.com> Message-ID: <1594659555-12669-12-git-send-email-wasim.khan@nxp.com> resource "config" is required to have minimum 1KB space. Signed-off-by: Wasim Khan --- drivers/pci/pcie_layerscape_gen4.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/pci/pcie_layerscape_gen4.c b/drivers/pci/pcie_layerscape_gen4.c index 0226bde..f9e3e04 100644 --- a/drivers/pci/pcie_layerscape_gen4.c +++ b/drivers/pci/pcie_layerscape_gen4.c @@ -455,6 +455,7 @@ static int ls_pcie_g4_probe(struct udevice *dev) u32 link_ctrl_sta; u32 val; int ret; + fdt_size_t cfg_size; pcie->bus = dev; @@ -488,6 +489,14 @@ static int ls_pcie_g4_probe(struct udevice *dev) return ret; } + cfg_size = fdt_resource_size(&pcie->cfg_res); + if (cfg_size < SZ_1K) { + printf("PCIe%d: %s Invalid size(0x%x) for resource \"config\", + expected minimum 0x%x \n", PCIE_SRDS_PRTCL(pcie->idx), + dev->name, cfg_size, SZ_1K); + return 0; + } + pcie->cfg = map_physmem(pcie->cfg_res.start, fdt_resource_size(&pcie->cfg_res), MAP_NOCACHE);