diff mbox series

[v3,2/5] fu540: prci: use common reset indexes defined in binding header

Message ID 1594370308-30957-3-git-send-email-sagar.kadam@sifive.com
State Accepted
Commit d2e43986373b75cdc00332106e6cca8bb5db452c
Headers show
Series add DM based reset driver for SiFive SoC's | expand

Commit Message

Sagar Shrikant Kadam July 10, 2020, 8:38 a.m. UTC 
Indexes of reset signals available in PRCI driver are also
defined in include/dt-bindings/reset/sifive-fu540-prci.h.
So use those instead of defining new ones again within the
fu540-prci driver.

Signed-off-by: Sagar Shrikant Kadam <sagar.kadam at sifive.com>
---
 drivers/clk/sifive/fu540-prci.c | 17 +++++++----------
 1 file changed, 7 insertions(+), 10 deletions(-)

Comments

Bin Meng July 21, 2020, 12:49 a.m. UTC | #1 
On Fri, Jul 10, 2020 at 4:39 PM Sagar Shrikant Kadam
<sagar.kadam@sifive.com> wrote:
>

> Indexes of reset signals available in PRCI driver are also

> defined in include/dt-bindings/reset/sifive-fu540-prci.h.

> So use those instead of defining new ones again within the

> fu540-prci driver.

>

> Signed-off-by: Sagar Shrikant Kadam <sagar.kadam@sifive.com>

> ---

>  drivers/clk/sifive/fu540-prci.c | 17 +++++++----------

>  1 file changed, 7 insertions(+), 10 deletions(-)

>


Reviewed-by: Bin Meng <bin.meng@windriver.com>
diff mbox series

Patch

diff --git a/drivers/clk/sifive/fu540-prci.c b/drivers/clk/sifive/fu540-prci.c
index fe6e0d4..00c31fc 100644
--- a/drivers/clk/sifive/fu540-prci.c
+++ b/drivers/clk/sifive/fu540-prci.c
@@ -41,6 +41,7 @@ 
 #include <linux/math64.h>
 #include <linux/clk/analogbits-wrpll-cln28hpc.h>
 #include <dt-bindings/clock/sifive-fu540-prci.h>
+#include <dt-bindings/reset/sifive-fu540-prci.h>
 
 /*
  * EXPECTED_CLK_PARENT_COUNT: how many parent clocks this driver expects:
@@ -131,21 +132,17 @@ 
 
 /* DEVICESRESETREG */
 #define PRCI_DEVICESRESETREG_OFFSET	0x28
-#define PRCI_DEVICESRESETREG_DDR_CTRL_RST_N_SHIFT 0
+
 #define PRCI_DEVICESRESETREG_DDR_CTRL_RST_N_MASK \
-			(0x1 << PRCI_DEVICESRESETREG_DDR_CTRL_RST_N_SHIFT)
-#define PRCI_DEVICESRESETREG_DDR_AXI_RST_N_SHIFT 1
+			(0x1 << PRCI_RST_DDR_CTRL_N)
 #define PRCI_DEVICESRESETREG_DDR_AXI_RST_N_MASK \
-			(0x1 << PRCI_DEVICESRESETREG_DDR_AXI_RST_N_SHIFT)
-#define PRCI_DEVICESRESETREG_DDR_AHB_RST_N_SHIFT 2
+			(0x1 << PRCI_RST_DDR_AXI_N)
 #define PRCI_DEVICESRESETREG_DDR_AHB_RST_N_MASK \
-			(0x1 << PRCI_DEVICESRESETREG_DDR_AHB_RST_N_SHIFT)
-#define PRCI_DEVICESRESETREG_DDR_PHY_RST_N_SHIFT 3
+			(0x1 << PRCI_RST_DDR_AHB_N)
 #define PRCI_DEVICESRESETREG_DDR_PHY_RST_N_MASK \
-			(0x1 << PRCI_DEVICESRESETREG_DDR_PHY_RST_N_SHIFT)
-#define PRCI_DEVICESRESETREG_GEMGXL_RST_N_SHIFT 5
+			(0x1 << PRCI_RST_DDR_PHY_N)
 #define PRCI_DEVICESRESETREG_GEMGXL_RST_N_MASK \
-			(0x1 << PRCI_DEVICESRESETREG_GEMGXL_RST_N_SHIFT)
+			(0x1 << PRCI_RST_GEMGXL_N)
 
 /* CLKMUXSTATUSREG */
 #define PRCI_CLKMUXSTATUSREG_OFFSET	0x2c