From patchwork Fri Jul 10 08:38:24 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sagar Shrikant Kadam X-Patchwork-Id: 241243 List-Id: U-Boot discussion From: sagar.kadam at sifive.com (Sagar Shrikant Kadam) Date: Fri, 10 Jul 2020 01:38:24 -0700 Subject: [PATCH v3 1/5] dt-bindings: prci: add indexes for reset signals available in prci In-Reply-To: <1594370308-30957-1-git-send-email-sagar.kadam@sifive.com> References: <1594370308-30957-1-git-send-email-sagar.kadam@sifive.com> Message-ID: <1594370308-30957-2-git-send-email-sagar.kadam@sifive.com> Add bit indexes for reset signals within the PRCI module on FU540-C000 SoC. The DDR and ethernet sub-system's have reset signals indicated by these reset indexes. Signed-off-by: Sagar Shrikant Kadam Reviewed-by: Bin Meng --- include/dt-bindings/reset/sifive-fu540-prci.h | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) create mode 100644 include/dt-bindings/reset/sifive-fu540-prci.h diff --git a/include/dt-bindings/reset/sifive-fu540-prci.h b/include/dt-bindings/reset/sifive-fu540-prci.h new file mode 100644 index 0000000..89aa5b6 --- /dev/null +++ b/include/dt-bindings/reset/sifive-fu540-prci.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2020 Sifive, Inc. + * Author: Sagar Kadam + */ + +#ifndef __DT_BINDINGS_RESET_SIFIVE_FU540_PRCI_H +#define __DT_BINDINGS_RESET_SIFIVE_FU540_PRCI_H + +/* Reset indexes for use by device tree data and the PRCI driver */ +#define PRCI_RST_DDR_CTRL_N 0 +#define PRCI_RST_DDR_AXI_N 1 +#define PRCI_RST_DDR_AHB_N 2 +#define PRCI_RST_DDR_PHY_N 3 +/* bit 4 is reserved bit */ +#define PRCI_RST_RSVD_N 4 +#define PRCI_RST_GEMGXL_N 5 + +#endif