From patchwork Tue Jun 9 03:28:26 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 241948 List-Id: U-Boot discussion From: bmeng.cn at gmail.com (Bin Meng) Date: Mon, 8 Jun 2020 20:28:26 -0700 Subject: [PATCH 2/2] riscv: fu540: dts: Correct reg size of otp and dmc nodes In-Reply-To: <1591673306-24315-1-git-send-email-bmeng.cn@gmail.com> References: <1591673306-24315-1-git-send-email-bmeng.cn@gmail.com> Message-ID: <1591673306-24315-2-git-send-email-bmeng.cn@gmail.com> From: Bin Meng Signed-off-by: Bin Meng Reviewed-by: Pragnesh Patel --- arch/riscv/dts/fu540-c000-u-boot.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/riscv/dts/fu540-c000-u-boot.dtsi b/arch/riscv/dts/fu540-c000-u-boot.dtsi index 0d3f710..35c153d 100644 --- a/arch/riscv/dts/fu540-c000-u-boot.dtsi +++ b/arch/riscv/dts/fu540-c000-u-boot.dtsi @@ -50,7 +50,7 @@ u-boot,dm-spl; otp: otp at 10070000 { compatible = "sifive,fu540-c000-otp"; - reg = <0x0 0x10070000 0x0 0x0FFF>; + reg = <0x0 0x10070000 0x0 0x1000>; fuse-count = <0x1000>; }; clint at 2000000 { @@ -63,7 +63,7 @@ compatible = "sifive,fu540-c000-ddr"; reg = <0x0 0x100b0000 0x0 0x0800 0x0 0x100b2000 0x0 0x2000 - 0x0 0x100b8000 0x0 0x0fff>; + 0x0 0x100b8000 0x0 0x1000>; clocks = <&prci PRCI_CLK_DDRPLL>; clock-frequency = <933333324>; u-boot,dm-spl;