From patchwork Thu Apr 30 13:00:05 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Madalin Bucur \(OSS\)" X-Patchwork-Id: 238988 List-Id: U-Boot discussion From: madalin.bucur at oss.nxp.com (Madalin Bucur) Date: Thu, 30 Apr 2020 16:00:05 +0300 Subject: [PATCH 08/19] powerpc: dts: add QorIQ DPAA 1 FMan interfaces to P4080DS In-Reply-To: <1588251616-14976-1-git-send-email-madalin.bucur@oss.nxp.com> References: <1588251616-14976-1-git-send-email-madalin.bucur@oss.nxp.com> Message-ID: <1588251616-14976-9-git-send-email-madalin.bucur@oss.nxp.com> Introduce the QorIQ DPAA 1 Frame Manager interfaces nodes in the P4080DS device tree. Signed-off-by: Madalin Bucur --- arch/powerpc/dts/p4080ds.dts | 191 ++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 190 insertions(+), 1 deletion(-) diff --git a/arch/powerpc/dts/p4080ds.dts b/arch/powerpc/dts/p4080ds.dts index 15a0f66..53c51d4 100644 --- a/arch/powerpc/dts/p4080ds.dts +++ b/arch/powerpc/dts/p4080ds.dts @@ -3,7 +3,7 @@ * P4080DS Device Tree Source * * Copyright 2011 - 2015 Freescale Semiconductor Inc. - * Copyright 2019 NXP + * Copyright 2019-2020 NXP */ /include/ "p4080.dtsi" @@ -15,4 +15,193 @@ #size-cells = <2>; interrupt-parent = <&mpic>; + aliases { + phy_rgmii = &phyrgmii; + phy5_slot3 = &phy5slot3; + phy6_slot3 = &phy6slot3; + phy7_slot3 = &phy7slot3; + phy8_slot3 = &phy8slot3; + emi1_slot3 = &p4080mdio2; + emi1_slot4 = &p4080mdio1; + emi1_slot5 = &p4080mdio3; + emi1_rgmii = &p4080mdio0; + emi2_slot4 = &p4080xmdio1; + emi2_slot5 = &p4080xmdio3; + }; + + soc: soc at ffe000000 { + ranges = <0x00000000 0xf 0xfe000000 0x1000000>; + reg = <0xf 0xfe000000 0 0x00001000>; + + fman at 400000 { + ethernet at e0000 { + phy-handle = <&phy0>; + phy-connection-type = "sgmii"; + }; + + ethernet at e2000 { + phy-handle = <&phy1>; + phy-connection-type = "sgmii"; + }; + + ethernet at e4000 { + phy-handle = <&phy2>; + phy-connection-type = "sgmii"; + }; + + ethernet at e6000 { + phy-handle = <&phy3>; + phy-connection-type = "sgmii"; + }; + + ethernet at f0000 { + phy-handle = <&phy10>; + phy-connection-type = "xgmii"; + }; + }; + + fman at 500000 { + ethernet at e0000 { + phy-handle = <&phy5>; + phy-connection-type = "sgmii"; + }; + + ethernet at e2000 { + phy-handle = <&phy6>; + phy-connection-type = "sgmii"; + }; + + ethernet at e4000 { + phy-handle = <&phy7>; + phy-connection-type = "sgmii"; + }; + + ethernet at e6000 { + phy-handle = <&phy8>; + phy-connection-type = "sgmii"; + }; + + ethernet at f0000 { + phy-handle = <&phy11>; + phy-connection-type = "xgmii"; + }; + }; + }; + + mdio-mux-emi1 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "mdio-mux-gpio", "mdio-mux"; + mdio-parent-bus = <&mdio0>; + gpios = <&gpio0 1 0>, <&gpio0 0 0>; + + p4080mdio0: mdio at 0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + phyrgmii: ethernet-phy at 0 { + reg = <0x0>; + }; + }; + + p4080mdio1: mdio at 1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + phy5: ethernet-phy at 1c { + reg = <0x1c>; + }; + + phy6: ethernet-phy at 1d { + reg = <0x1d>; + }; + + phy7: ethernet-phy at 1e { + reg = <0x1e>; + }; + + phy8: ethernet-phy at 1f { + reg = <0x1f>; + }; + }; + + p4080mdio2: mdio at 2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + status = "disabled"; + + phy5slot3: ethernet-phy at 1c { + reg = <0x1c>; + }; + + phy6slot3: ethernet-phy at 1d { + reg = <0x1d>; + }; + + phy7slot3: ethernet-phy at 1e { + reg = <0x1e>; + }; + + phy8slot3: ethernet-phy at 1f { + reg = <0x1f>; + }; + }; + + p4080mdio3: mdio at 3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + + phy0: ethernet-phy at 1c { + reg = <0x1c>; + }; + + phy1: ethernet-phy at 1d { + reg = <0x1d>; + }; + + phy2: ethernet-phy at 1e { + reg = <0x1e>; + }; + + phy3: ethernet-phy at 1f { + reg = <0x1f>; + }; + }; + }; + + mdio-mux-emi2 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "mdio-mux-gpio", "mdio-mux"; + mdio-parent-bus = <&xmdio0>; + gpios = <&gpio0 3 0>, <&gpio0 2 0>; + + p4080xmdio1: mdio at 1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + phy11: ethernet-phy at 0 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <0x0>; + }; + }; + + p4080xmdio3: mdio at 3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + + phy10: ethernet-phy at 4 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <0x4>; + }; + }; + }; }; + +/include/ "p4080si-post.dtsi"