From patchwork Sat Mar 28 09:43:51 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stefan Bosch X-Patchwork-Id: 244456 List-Id: U-Boot discussion From: stefan_b at posteo.net (Stefan Bosch) Date: Sat, 28 Mar 2020 10:43:51 +0100 Subject: [RFC PATCH v2 08/13] video: add nexell video driver (soc: mlc, mipi) In-Reply-To: <1585388636-5404-1-git-send-email-stefan_b@posteo.net> References: <1585388636-5404-1-git-send-email-stefan_b@posteo.net> Message-ID: <1585388636-5404-9-git-send-email-stefan_b@posteo.net> Low level functions for MLC (Multi Layer Control) and MIPI (Mobile Industry Processor Interface). Signed-off-by: Stefan Bosch --- Changes in v2: None drivers/video/nexell/soc/s5pxx18_soc_mipi.c | 580 +++++++++ drivers/video/nexell/soc/s5pxx18_soc_mipi.h | 291 +++++ drivers/video/nexell/soc/s5pxx18_soc_mlc.c | 1861 +++++++++++++++++++++++++++ drivers/video/nexell/soc/s5pxx18_soc_mlc.h | 429 ++++++ 4 files changed, 3161 insertions(+) create mode 100644 drivers/video/nexell/soc/s5pxx18_soc_mipi.c create mode 100644 drivers/video/nexell/soc/s5pxx18_soc_mipi.h create mode 100644 drivers/video/nexell/soc/s5pxx18_soc_mlc.c create mode 100644 drivers/video/nexell/soc/s5pxx18_soc_mlc.h diff --git a/drivers/video/nexell/soc/s5pxx18_soc_mipi.c b/drivers/video/nexell/soc/s5pxx18_soc_mipi.c new file mode 100644 index 0000000..1000ddb --- /dev/null +++ b/drivers/video/nexell/soc/s5pxx18_soc_mipi.c @@ -0,0 +1,580 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2016 Nexell Co., Ltd. + * + * Author: junghyun, kim + */ + +#include +#include + +#include "s5pxx18_soc_disptop.h" +#include "s5pxx18_soc_mipi.h" + +static struct nx_mipi_register_set *__g_pregister[NUMBER_OF_MIPI_MODULE]; + +int nx_mipi_smoke_test(u32 module_index) +{ + register struct nx_mipi_register_set *pregister; + + pregister = __g_pregister[module_index]; + + if (pregister->csis_config_ch0 != 0x000000FC) + return false; + + if (pregister->dsim_intmsk != 0xB337FFFF) + return false; + + writel(0xDEADC0DE, &pregister->csis_dphyctrl); + writel(0xFFFFFFFF, &pregister->csis_ctrl2); + writel(0xDEADC0DE, &pregister->dsim_msync); + + if (pregister->csis_dphyctrl != 0xDE80001E) + return false; + + if ((pregister->csis_ctrl2 & (~1)) != 0xEEE00010) + return false; + + if (pregister->dsim_msync != 0xDE80C0DE) + return false; + + return true; +} + +void nx_mipi_set_base_address(u32 module_index, void *base_address) +{ + __g_pregister[module_index] = + (struct nx_mipi_register_set *)base_address; +} + +void *nx_mipi_get_base_address(u32 module_index) +{ + return (void *)__g_pregister[module_index]; +} + +u32 nx_mipi_get_physical_address(u32 module_index) +{ + const u32 physical_addr[] = PHY_BASEADDR_MIPI_LIST; + + return physical_addr[module_index]; +} + +#define __nx_mipi_valid_dsi_intmask__ \ + (~((1 << 26) | (1 << 23) | (1 << 22) | (1 << 19))) + +void nx_mipi_set_interrupt_enable(u32 module_index, u32 int_num, int enable) +{ + register struct nx_mipi_register_set *pregister; + register u32 regvalue; + + pregister = __g_pregister[module_index]; + if (int_num < 32) { + regvalue = pregister->csis_intmsk; + regvalue &= ~(1ul << int_num); + regvalue |= (u32)enable << int_num; + writel(regvalue, &pregister->csis_intmsk); + } else { + regvalue = pregister->dsim_intmsk; + regvalue &= ~(1ul << (int_num - 32)); + regvalue |= (u32)enable << (int_num - 32); + writel(regvalue, &pregister->dsim_intmsk); + } +} + +int nx_mipi_get_interrupt_enable(u32 module_index, u32 int_num) +{ + if (int_num < 32) + return (int)((__g_pregister[module_index]->csis_intmsk >> + int_num) & 0x01); + else + return (int)((__g_pregister[module_index]->dsim_intmsk >> + (int_num - 32)) & 0x01); +} + +int nx_mipi_get_interrupt_pending(u32 module_index, u32 int_num) +{ + register struct nx_mipi_register_set *pregister; + register u32 regvalue; + int ret; + + pregister = __g_pregister[module_index]; + if (int_num < 32) { + regvalue = pregister->csis_intmsk; + regvalue &= pregister->csis_intsrc; + ret = (int)((regvalue >> int_num) & 0x01); + } else { + regvalue = pregister->dsim_intmsk; + regvalue &= pregister->dsim_intsrc; + ret = (int)((regvalue >> (int_num - 32)) & 0x01); + } + + return ret; +} + +void nx_mipi_clear_interrupt_pending(u32 module_index, u32 int_num) +{ + register struct nx_mipi_register_set *pregister; + + pregister = __g_pregister[module_index]; + if (int_num < 32) + writel(1ul << int_num, &pregister->csis_intsrc); + else + writel(1ul << (int_num - 32), &pregister->dsim_intsrc); +} + +void nx_mipi_set_interrupt_enable_all(u32 module_index, int enable) +{ + register struct nx_mipi_register_set *pregister; + + pregister = __g_pregister[module_index]; + if (enable) + writel(__nx_mipi_valid_dsi_intmask__, &pregister->dsim_intmsk); + else + writel(0, &pregister->dsim_intmsk); +} + +int nx_mipi_get_interrupt_enable_all(u32 module_index) +{ + if (__g_pregister[module_index]->csis_intmsk) + return true; + + if (__g_pregister[module_index]->dsim_intmsk) + return true; + + return false; +} + +int nx_mipi_get_interrupt_pending_all(u32 module_index) +{ + register struct nx_mipi_register_set *pregister; + register u32 regvalue; + + pregister = __g_pregister[module_index]; + regvalue = pregister->csis_intmsk; + regvalue &= pregister->csis_intsrc; + + if (regvalue) + return true; + + regvalue = pregister->dsim_intmsk; + regvalue &= pregister->dsim_intsrc; + + if (regvalue) + return true; + + return false; +} + +void nx_mipi_clear_interrupt_pending_all(u32 module_index) +{ + register struct nx_mipi_register_set *pregister; + + pregister = __g_pregister[module_index]; + writel(__nx_mipi_valid_dsi_intmask__, &pregister->dsim_intsrc); +} + +int32_t nx_mipi_get_interrupt_pending_number(u32 module_index) +{ + register struct nx_mipi_register_set *pregister; + register u32 regvalue; + int i; + + pregister = __g_pregister[module_index]; + regvalue = pregister->csis_intmsk; + regvalue &= pregister->csis_intsrc; + if (regvalue != 0) { + for (i = 0; i < 32; i++) { + if (regvalue & 1ul) + return i; + regvalue >>= 1; + } + } + + regvalue = pregister->dsim_intmsk; + regvalue &= pregister->dsim_intsrc; + if (regvalue != 0) { + for (i = 0; i < 32; i++) { + if (regvalue & 1ul) + return i + 32; + regvalue >>= 1; + } + } + return -1; +} + +#define writereg(regname, mask, value) \ + regvalue = pregister->(regname); \ + regvalue = (regvalue & (~(mask))) | (value); \ + writel(regvalue, &pregister->(regname)) + +void nx_mipi_dsi_get_status(u32 module_index, u32 *pulps, u32 *pstop, + u32 *pispllstable, u32 *pisinreset, + u32 *pisbackward, u32 *pishsclockready) +{ + register struct nx_mipi_register_set *pregister; + register u32 regvalue; + + pregister = __g_pregister[module_index]; + regvalue = pregister->dsim_status; + if (pulps) { + *pulps = 0; + if (regvalue & (1 << 4)) + *pulps |= (1 << 0); + if (regvalue & (1 << 5)) + *pulps |= (1 << 1); + if (regvalue & (1 << 6)) + *pulps |= (1 << 2); + if (regvalue & (1 << 7)) + *pulps |= (1 << 3); + if (regvalue & (1 << 9)) + *pulps |= (1 << 4); + } + + if (pstop) { + *pstop = 0; + if (regvalue & (1 << 0)) + *pstop |= (1 << 0); + if (regvalue & (1 << 1)) + *pstop |= (1 << 1); + if (regvalue & (1 << 2)) + *pstop |= (1 << 2); + if (regvalue & (1 << 3)) + *pstop |= (1 << 3); + if (regvalue & (1 << 8)) + *pstop |= (1 << 4); + } + + if (pispllstable) + *pispllstable = (regvalue >> 31) & 1; + + if (pisinreset) + *pisinreset = ((regvalue >> 20) & 1) ? 0 : 1; + + if (pisbackward) + *pisbackward = (regvalue >> 16) & 1; + + if (pishsclockready) + *pishsclockready = (regvalue >> 10) & 1; +} + +void nx_mipi_dsi_software_reset(u32 module_index) +{ + register struct nx_mipi_register_set *pregister; + + pregister = __g_pregister[module_index]; + + writel(0x00010001, &pregister->dsim_swrst); + + while (0 != (readl(&pregister->dsim_status) & (1 << 20))) + ; + + writel(0x00000000, &pregister->dsim_swrst); +} + +void nx_mipi_dsi_set_clock(u32 module_index, int enable_txhsclock, + int use_external_clock, int enable_byte_clock, + int enable_escclock_clock_lane, + int enable_escclock_data_lane0, + int enable_escclock_data_lane1, + int enable_escclock_data_lane2, + int enable_escclock_data_lane3, + int enable_escprescaler, u32 escprescalervalue) +{ + register struct nx_mipi_register_set *pregister; + register u32 regvalue; + + pregister = __g_pregister[module_index]; + regvalue = 0; + regvalue |= (enable_txhsclock << 31); + regvalue |= (use_external_clock << 27); + regvalue |= (enable_byte_clock << 24); + regvalue |= (enable_escclock_clock_lane << 19); + regvalue |= (enable_escclock_data_lane0 << 20); + regvalue |= (enable_escclock_data_lane1 << 21); + regvalue |= (enable_escclock_data_lane2 << 22); + regvalue |= (enable_escclock_data_lane3 << 23); + regvalue |= (enable_escprescaler << 28); + regvalue |= escprescalervalue; + + writel(regvalue, &pregister->dsim_clkctrl); +} + +void nx_mipi_dsi_set_timeout(u32 module_index, u32 bta_tout, u32 lpdrtout) +{ + register struct nx_mipi_register_set *pregister; + register u32 regvalue; + + pregister = __g_pregister[module_index]; + regvalue = 0; + regvalue |= (bta_tout << 16); + regvalue |= (lpdrtout << 0); + + writel(regvalue, &pregister->dsim_timeout); +} + +void nx_mipi_dsi_set_config_video_mode(u32 module_index, + int enable_auto_flush_main_display_fifo, + int enable_auto_vertical_count, + int enable_burst, + enum nx_mipi_dsi_syncmode sync_mode, + int enable_eo_tpacket, + int enable_hsync_end_packet, + int enable_hfp, int enable_hbp, + int enable_hsa, + u32 number_of_virtual_channel, + enum nx_mipi_dsi_format format, + u32 number_of_words_in_hfp, + u32 number_of_words_in_hbp, + u32 number_of_words_in_hsync, + u32 number_of_lines_in_vfp, + u32 number_of_lines_in_vbp, + u32 number_of_lines_in_vsync, + u32 number_of_lines_in_command_allow) +{ + register struct nx_mipi_register_set *pregister; + register u32 regvalue; + u32 newvalue; + + pregister = __g_pregister[module_index]; + newvalue = (1 << 25); + newvalue |= ((1 - enable_auto_flush_main_display_fifo) << 29); + newvalue |= (enable_auto_vertical_count << 24); + newvalue |= (enable_burst << 26); + newvalue |= (sync_mode << 27); + newvalue |= ((1 - enable_eo_tpacket) << 28); + newvalue |= (enable_hsync_end_packet << 23); + newvalue |= ((1 - enable_hfp) << 22); + newvalue |= ((1 - enable_hbp) << 21); + newvalue |= ((1 - enable_hsa) << 20); + newvalue |= (number_of_virtual_channel << 18); + newvalue |= (format << 12); + + writereg(dsim_config, 0xFFFFFF00, newvalue); + + newvalue = (number_of_lines_in_command_allow << 28); + newvalue |= (number_of_lines_in_vfp << 16); + newvalue |= (number_of_lines_in_vbp << 0); + + writel(newvalue, &pregister->dsim_mvporch); + + newvalue = (number_of_words_in_hfp << 16); + newvalue |= (number_of_words_in_hbp << 0); + + writel(newvalue, &pregister->dsim_mhporch); + + newvalue = (number_of_words_in_hsync << 0); + newvalue |= (number_of_lines_in_vsync << 22); + + writel(newvalue, &pregister->dsim_msync); +} + +void nx_mipi_dsi_set_config_command_mode(u32 module_index, + int + enable_auto_flush_main_display_fifo, + int enable_eo_tpacket, + u32 number_of_virtual_channel, + enum nx_mipi_dsi_format format) +{ + register struct nx_mipi_register_set *pregister; + register u32 regvalue; + u32 newvalue; + + pregister = __g_pregister[module_index]; + newvalue = (0 << 25); + newvalue |= (enable_auto_flush_main_display_fifo << 29); + newvalue |= (enable_eo_tpacket << 28); + newvalue |= (number_of_virtual_channel << 18); + newvalue |= (format << 12); + writereg(dsim_config, 0xFFFFFF00, newvalue); +} + +void nx_mipi_dsi_set_escape_mode(u32 module_index, u32 stop_state_count, + int force_stop_state, int force_bta, + enum nx_mipi_dsi_lpmode cmdin_lp, + enum nx_mipi_dsi_lpmode txinlp) +{ + register struct nx_mipi_register_set *pregister; + register u32 regvalue; + u32 newvalue; + + pregister = __g_pregister[module_index]; + newvalue = (stop_state_count << 21); + newvalue |= (force_stop_state << 20); + newvalue |= (force_bta << 16); + newvalue |= (cmdin_lp << 7); + newvalue |= (txinlp << 6); + writereg(dsim_escmode, 0xFFFFFFC0, newvalue); +} + +void nx_mipi_dsi_set_escape_lp(u32 module_index, + enum nx_mipi_dsi_lpmode cmdin_lp, + enum nx_mipi_dsi_lpmode txinlp) +{ + register struct nx_mipi_register_set *pregister; + register u32 regvalue; + u32 newvalue = 0; + + pregister = __g_pregister[module_index]; + newvalue |= (cmdin_lp << 7); + newvalue |= (txinlp << 6); + writereg(dsim_escmode, 0xC0, newvalue); +} + +void nx_mipi_dsi_remote_reset_trigger(u32 module_index) +{ + register struct nx_mipi_register_set *pregister; + register u32 regvalue; + u32 newvalue; + + pregister = __g_pregister[module_index]; + newvalue = (1 << 4); + writereg(dsim_escmode, (1 << 4), newvalue); + + while (readl(&pregister->dsim_escmode) & (1 << 4)) + ; +} + +void nx_mipi_dsi_set_ulps(u32 module_index, int ulpsclocklane, int ulpsdatalane) +{ + register struct nx_mipi_register_set *pregister; + register u32 regvalue; + + pregister = __g_pregister[module_index]; + regvalue = pregister->dsim_escmode; + + if (ulpsclocklane) { + regvalue &= ~(1 << 0); + regvalue |= (1 << 1); + } else { + regvalue |= (1 << 0); + } + + if (ulpsdatalane) { + regvalue &= ~(1 << 2); + regvalue |= (1 << 3); + } else { + regvalue |= (1 << 2); + } + + writel(regvalue, &pregister->dsim_escmode); + + if (ulpsclocklane) + while ((1 << 9) == + (readl(&pregister->dsim_status) & (1 << 9))) + ; + else + while (0 != (readl(&pregister->dsim_status) & (1 << 9))) + ; + + if (ulpsdatalane) + while ((15 << 4) == + (readl(&pregister->dsim_status) & (15 << 4))) + ; + else + while (0 != (readl(&pregister->dsim_status) & (15 << 4))) + ; + + if (!ulpsclocklane) + regvalue &= (3 << 0); + + if (!ulpsdatalane) + regvalue |= (3 << 2); + + writel(regvalue, &pregister->dsim_escmode); +} + +void nx_mipi_dsi_set_size(u32 module_index, u32 width, u32 height) +{ + register struct nx_mipi_register_set *pregister; + register u32 regvalue; + u32 newvalue; + + pregister = __g_pregister[module_index]; + newvalue = (height << 16); + newvalue |= (width << 0); + writereg(dsim_mdresol, 0x0FFFFFFF, newvalue); +} + +void nx_mipi_dsi_set_enable(u32 module_index, int enable) +{ + register struct nx_mipi_register_set *pregister; + register u32 regvalue; + + pregister = __g_pregister[module_index]; + writereg(dsim_mdresol, (1 << 31), (enable << 31)); +} + +void nx_mipi_dsi_set_phy(u32 module_index, u32 number_of_data_lanes, + int enable_clock_lane, int enable_data_lane0, + int enable_data_lane1, int enable_data_lane2, + int enable_data_lane3, int swap_clock_lane, + int swap_data_lane) +{ + register struct nx_mipi_register_set *pregister; + register u32 regvalue; + u32 newvalue; + + pregister = __g_pregister[module_index]; + newvalue = (number_of_data_lanes << 5); + newvalue |= (enable_clock_lane << 0); + newvalue |= (enable_data_lane0 << 1); + newvalue |= (enable_data_lane1 << 2); + newvalue |= (enable_data_lane2 << 3); + newvalue |= (enable_data_lane3 << 4); + writereg(dsim_config, 0xFF, newvalue); + newvalue = (swap_clock_lane << 1); + newvalue |= (swap_data_lane << 0); + writereg(dsim_phyacchr1, 0x3, newvalue); +} + +void nx_mipi_dsi_set_pll(u32 module_index, int enable, u32 pllstabletimer, + u32 m_pllpms, u32 m_bandctl, u32 m_dphyctl, + u32 b_dphyctl) +{ + register struct nx_mipi_register_set *pregister; + register u32 regvalue; + u32 newvalue; + + pregister = __g_pregister[module_index]; + if (!enable) { + newvalue = (enable << 23); + newvalue |= (m_pllpms << 1); + newvalue |= (m_bandctl << 24); + writereg(dsim_pllctrl, 0x0FFFFFFF, newvalue); + } + + writel(m_dphyctl, &pregister->dsim_phyacchr); + writel(pllstabletimer, &pregister->dsim_plltmr); + writel((b_dphyctl << 9), &pregister->dsim_phyacchr1); + + if (enable) { + newvalue = (enable << 23); + newvalue |= (m_pllpms << 1); + newvalue |= (m_bandctl << 24); + writereg(dsim_pllctrl, 0x0FFFFFFF, newvalue); + } +} + +void nx_mipi_dsi_write_pkheader(u32 module_index, u32 data) +{ + register struct nx_mipi_register_set *pregister; + + pregister = __g_pregister[module_index]; + writel(data, &pregister->dsim_pkthdr); +} + +void nx_mipi_dsi_write_payload(u32 module_index, u32 data) +{ + register struct nx_mipi_register_set *pregister; + + pregister = __g_pregister[module_index]; + writel(data, &pregister->dsim_payload); +} + +u32 nx_mipi_dsi_read_fifo_status(u32 module_index) +{ + register struct nx_mipi_register_set *pregister; + + pregister = __g_pregister[module_index]; + return readl(&pregister->dsim_fifoctrl); +} diff --git a/drivers/video/nexell/soc/s5pxx18_soc_mipi.h b/drivers/video/nexell/soc/s5pxx18_soc_mipi.h new file mode 100644 index 0000000..63751ca --- /dev/null +++ b/drivers/video/nexell/soc/s5pxx18_soc_mipi.h @@ -0,0 +1,291 @@ +/* SPDX-License-Identifier: GPL-2.0+ + * + * Copyright (C) 2016 Nexell Co., Ltd. + * + * Author: junghyun, kim + */ + +#ifndef _S5PXX18_SOC_MIPI_H_ +#define _S5PXX18_SOC_MIPI_H_ + +#define NUMBER_OF_MIPI_MODULE 1 +#define PHY_BASEADDR_MIPI_MODULE 0xC00D0000 +#define PHY_BASEADDR_MIPI_LIST \ + { PHY_BASEADDR_MIPI_MODULE } + +#define nx_mipi_numberof_csi_channels 2 + +struct nx_mipi_register_set { + u32 csis_control; + u32 csis_dphyctrl; + u32 csis_config_ch0; + u32 csis_dphysts; + u32 csis_intmsk; + u32 csis_intsrc; + u32 csis_ctrl2; + u32 csis_version; + u32 csis_dphyctrl_0; + u32 csis_dphyctrl_1; + u32 __reserved0; + u32 csis_resol_ch0; + u32 __reserved1; + u32 __reserved2; + u32 sdw_config_ch0; + u32 sdw_resol_ch0; + u32 csis_config_ch1; + u32 csis_resol_ch1; + u32 sdw_config_ch1; + u32 sdw_resol_ch1; + u32 csis_config_ch2; + u32 csis_resol_ch2; + u32 sdw_config_ch2; + u32 sdw_resol_ch2; + u32 csis_config_ch3; + u32 csis_resol_ch3; + u32 sdw_config_ch3; + u32 sdw_resol_3; + u32 __reserved3[(16 + 128) / 4]; + + u32 dsim_status; + u32 dsim_swrst; + u32 dsim_clkctrl; + u32 dsim_timeout; + u32 dsim_config; + u32 dsim_escmode; + u32 dsim_mdresol; + u32 dsim_mvporch; + u32 dsim_mhporch; + u32 dsim_msync; + u32 dsim_sdresol; + u32 dsim_intsrc; + u32 dsim_intmsk; + u32 dsim_pkthdr; + u32 dsim_payload; + u32 dsim_rxfifo; + u32 dsim_fifothld; + u32 dsim_fifoctrl; + u32 dsim_memacchr; + u32 dsim_pllctrl; + u32 dsim_plltmr; + u32 dsim_phyacchr; + u32 dsim_phyacchr1; + + u32 __reserved4[(0x2000 - 0x015C) / 4]; + u32 mipi_csis_pktdata[0x2000 / 4]; +}; + +enum nx_mipi_dsi_syncmode { + nx_mipi_dsi_syncmode_event = 0, + nx_mipi_dsi_syncmode_pulse = 1, +}; + +enum nx_mipi_dsi_format { + nx_mipi_dsi_format_command3 = 0, + nx_mipi_dsi_format_command8 = 1, + nx_mipi_dsi_format_command12 = 2, + nx_mipi_dsi_format_command16 = 3, + nx_mipi_dsi_format_rgb565 = 4, + nx_mipi_dsi_format_rgb666_packed = 5, + nx_mipi_dsi_format_rgb666 = 6, + nx_mipi_dsi_format_rgb888 = 7 +}; + +enum nx_mipi_dsi_lpmode { + nx_mipi_dsi_lpmode_hs = 0, + nx_mipi_dsi_lpmode_lp = 1 +}; + +enum nx_mipi_phy_b_dphyctl { + nx_mipi_phy_b_dphyctl_m_txclkesc_20_mhz = 0x1F4, + nx_mipi_phy_b_dphyctl_m_txclkesc_19_mhz = 0x1DB, + nx_mipi_phy_b_dphyctl_m_txclkesc_18_mhz = 0x1C2, + nx_mipi_phy_b_dphyctl_m_txclkesc_17_mhz = 0x1A9, + nx_mipi_phy_b_dphyctl_m_txclkesc_16_mhz = 0x190, + nx_mipi_phy_b_dphyctl_m_txclkesc_15_mhz = 0x177, + nx_mipi_phy_b_dphyctl_m_txclkesc_14_mhz = 0x15E, + nx_mipi_phy_b_dphyctl_m_txclkesc_13_mhz = 0x145, + nx_mipi_phy_b_dphyctl_m_txclkesc_12_mhz = 0x12C, + nx_mipi_phy_b_dphyctl_m_txclkesc_11_mhz = 0x113, + nx_mipi_phy_b_dphyctl_m_txclkesc_10_mhz = 0x0FA, + nx_mipi_phy_b_dphyctl_m_txclkesc_9_mhz = 0x0E1, + nx_mipi_phy_b_dphyctl_m_txclkesc_8_mhz = 0x0C8, + nx_mipi_phy_b_dphyctl_m_txclkesc_7_mhz = 0x0AF, + nx_mipi_phy_b_dphyctl_m_txclkesc_6_mhz = 0x096, + nx_mipi_phy_b_dphyctl_m_txclkesc_5_mhz = 0x07D, + nx_mipi_phy_b_dphyctl_m_txclkesc_4_mhz = 0x064, + nx_mipi_phy_b_dphyctl_m_txclkesc_3_mhz = 0x04B, + nx_mipi_phy_b_dphyctl_m_txclkesc_2_mhz = 0x032, + nx_mipi_phy_b_dphyctl_m_txclkesc_1_mhz = 0x019, + nx_mipi_phy_b_dphyctl_m_txclkesc_0_10_mhz = 0x003, + nx_mipi_phy_b_dphyctl_m_txclkesc_0_01_mhz = 0x000 +}; + +enum { + nx_mipi_rst = 0, + nx_mipi_rst_dsi_i, + nx_mipi_rst_csi_i, + nx_mipi_rst_phy_s, + nx_mipi_rst_phy_m +}; + +enum nx_mipi_int { + nx_mipi_int_csi_even_before = 31, + nx_mipi_int_csi_even_after = 30, + nx_mipi_int_csi_odd_before = 29, + nx_mipi_int_csi_odd_after = 28, + nx_mipi_int_csi_frame_start_ch3 = 27, + nx_mipi_int_csi_frame_start_ch2 = 26, + nx_mipi_int_csi_frame_start_ch1 = 25, + nx_mipi_int_csi_frame_start_ch0 = 24, + nx_mipi_int_csi_frame_end_ch3 = 23, + nx_mipi_int_csi_frame_end_ch2 = 22, + nx_mipi_int_csi_frame_end_ch1 = 21, + nx_mipi_int_csi_frame_end_ch0 = 20, + nx_mipi_int_csi_err_sot_hs_ch3 = 19, + nx_mipi_int_csi_err_sot_hs_ch2 = 18, + nx_mipi_int_csi_err_sot_hs_ch1 = 17, + nx_mipi_int_csi_err_sot_hs_ch0 = 16, + nx_mipi_int_csi_err_lost_fs_ch3 = 15, + nx_mipi_int_csi_err_lost_fs_ch2 = 14, + nx_mipi_int_csi_err_lost_fs_ch1 = 13, + nx_mipi_int_csi_err_lost_fs_ch0 = 12, + nx_mipi_int_csi_err_lost_fe_ch3 = 11, + nx_mipi_int_csi_err_lost_fe_ch2 = 10, + nx_mipi_int_csi_err_lost_fe_ch1 = 9, + nx_mipi_int_csi_err_lost_fe_ch0 = 8, + nx_mipi_int_csi_err_over_ch3 = 7, + nx_mipi_int_csi_err_over_ch2 = 6, + nx_mipi_int_csi_err_over_ch1 = 5, + nx_mipi_int_csi_err_over_ch0 = 4, + + nx_mipi_int_csi_err_ecc = 2, + nx_mipi_int_csi_err_crc = 1, + nx_mipi_int_csi_err_id = 0, + nx_mipi_int_dsi_pll_stable = 32 + 31, + nx_mipi_int_dsi_sw_rst_release = 32 + 30, + nx_mipi_int_dsi_sfrplfifoempty = 32 + 29, + nx_mipi_int_dsi_sfrphfifoempty = 32 + 28, + nx_mipi_int_dsi_sync_override = 32 + 27, + + nx_mipi_int_dsi_bus_turn_over = 32 + 25, + nx_mipi_int_dsi_frame_done = 32 + 24, + + nx_mipi_int_dsi_lpdr_tout = 32 + 21, + nx_mipi_int_dsi_ta_tout = 32 + 20, + + nx_mipi_int_dsi_rx_dat_done = 32 + 18, + nx_mipi_int_dsi_rx_te = 32 + 17, + nx_mipi_int_dsi_rx_ack = 32 + 16, + nx_mipi_int_dsi_err_rx_ecc = 32 + 15, + nx_mipi_int_dsi_err_rx_crc = 32 + 14, + nx_mipi_int_dsi_err_esc3 = 32 + 13, + nx_mipi_int_dsi_err_esc2 = 32 + 12, + nx_mipi_int_dsi_err_esc1 = 32 + 11, + nx_mipi_int_dsi_err_esc0 = 32 + 10, + nx_mipi_int_dsi_err_sync3 = 32 + 9, + nx_mipi_int_dsi_err_sync2 = 32 + 8, + nx_mipi_int_dsi_err_sync1 = 32 + 7, + nx_mipi_int_dsi_err_sync0 = 32 + 6, + nx_mipi_int_dsi_err_control3 = 32 + 5, + nx_mipi_int_dsi_err_control2 = 32 + 4, + nx_mipi_int_dsi_err_control1 = 32 + 3, + nx_mipi_int_dsi_err_control0 = 32 + 2, + nx_mipi_int_dsi_err_content_lp0 = 32 + 1, + nx_mipi_int_dsi_err_content_lp1 = 32 + 0, +}; + +#define DSI_TX_FIFO_SIZE 2048 +#define DSI_RX_FIFO_SIZE 256 +#define DSI_RX_FIFO_EMPTY 0x30800002 + +void nx_mipi_dsi_get_status(u32 module_index, u32 *pulps, u32 *pstop, + u32 *pispllstable, u32 *pisinreset, + u32 *pisbackward, u32 *pishsclockready); + +void nx_mipi_dsi_software_reset(u32 module_index); + +void nx_mipi_dsi_set_clock(u32 module_index, int enable_txhsclock, + int use_external_clock, int enable_byte_clock, + int enable_escclock_clock_lane, + int enable_escclock_data_lane0, + int enable_escclock_data_lane1, + int enable_escclock_data_lane2, + int enable_escclock_data_lane3, + int enable_escprescaler, + u32 escprescalervalue); + +void nx_mipi_dsi_set_timeout(u32 module_index, u32 bta_tout, + u32 lpdrtout); + +void nx_mipi_dsi_set_config_video_mode(u32 module_index, + int enable_auto_flush_main_display_fifo, + int enable_auto_vertical_count, + int enable_burst, + enum nx_mipi_dsi_syncmode + sync_mode, int enable_eo_tpacket, + int enable_hsync_end_packet, + int enable_hfp, int enable_hbp, + int enable_hsa, + u32 number_of_virtual_channel, + enum nx_mipi_dsi_format format, + u32 number_of_words_in_hfp, + u32 number_of_words_in_hbp, + u32 number_of_words_in_hsync, + u32 number_of_lines_in_vfp, + u32 number_of_lines_in_vbp, + u32 number_of_lines_in_vsync, + u32 number_of_lines_in_command_allow); + +void nx_mipi_dsi_set_config_command_mode(u32 module_index, + int enable_auto_flush_main_display_fifo, + int enable_eo_tpacket, + u32 number_of_virtual_channel, + enum nx_mipi_dsi_format format); + +void nx_mipi_dsi_set_escape_mode(u32 module_index, u32 stop_state_count, + int force_stop_state, int force_bta, + enum nx_mipi_dsi_lpmode cmdin_lp, + enum nx_mipi_dsi_lpmode txinlp); +void nx_mipi_dsi_set_escape_lp(u32 module_index, + enum nx_mipi_dsi_lpmode cmdin_lp, + enum nx_mipi_dsi_lpmode txinlp); + +void nx_mipi_dsi_remote_reset_trigger(u32 module_index); +void nx_mipi_dsi_set_ulps(u32 module_index, int ulpsclocklane, + int ulpsdatalane); +void nx_mipi_dsi_set_size(u32 module_index, u32 width, u32 height); +void nx_mipi_dsi_set_enable(u32 module_index, int enable); +void nx_mipi_dsi_set_phy(u32 module_index, u32 number_of_data_lanes, + int enable_clock_lane, int enable_data_lane0, + int enable_data_lane1, int enable_data_lane2, + int enable_data_lane3, int swap_clock_lane, + int swap_data_lane); + +void nx_mipi_dsi_set_pll(u32 module_index, int enable, + u32 pllstabletimer, u32 m_pllpms, u32 m_bandctl, + u32 m_dphyctl, u32 b_dphyctl); + +void nx_mipi_dsi_write_pkheader(u32 module_index, u32 data); +void nx_mipi_dsi_write_payload(u32 module_index, u32 data); +u32 nx_mipi_dsi_read_fifo(u32 module_index); +u32 nx_mipi_dsi_read_fifo_status(u32 module_index); + +int nx_mipi_smoke_test(u32 module_index); +void nx_mipi_set_base_address(u32 module_index, void *base_address); +void *nx_mipi_get_base_address(u32 module_index); +u32 nx_mipi_get_physical_address(u32 module_index); + +void nx_mipi_dsi_set_interrupt_enable_all(u32 module_index, int enable); +void nx_mipi_dsi_set_interrupt_enable(u32 module_index, + u32 int_num, int enable); +int nx_mipi_dsi_get_interrupt_enable(u32 module_index, u32 int_num); +int nx_mipi_dsi_get_interrupt_enable_all(u32 module_index); + +int nx_mipi_dsi_get_interrupt_pending(u32 module_index, u32 int_num); +int nx_mipi_dsi_get_interrupt_pending_all(u32 module_index); +int32_t nx_mipi_dsi_get_interrupt_pending_number(u32 module_index); + +void nx_mipi_dsi_clear_interrupt_pending(u32 module_index, u32 int_num); +void nx_mipi_dsi_clear_interrupt_pending_all(u32 module_index); + +#endif diff --git a/drivers/video/nexell/soc/s5pxx18_soc_mlc.c b/drivers/video/nexell/soc/s5pxx18_soc_mlc.c new file mode 100644 index 0000000..c8cf833 --- /dev/null +++ b/drivers/video/nexell/soc/s5pxx18_soc_mlc.c @@ -0,0 +1,1861 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2016 Nexell Co., Ltd. + * + * Author: junghyun, kim + */ + +#include +#include + +#include "s5pxx18_soc_mlc.h" + +static struct { + struct nx_mlc_register_set *pregister; +} __g_module_variables[NUMBER_OF_MLC_MODULE] = { { NULL, },}; + +int nx_mlc_initialize(void) +{ + static int binit; + u32 i; + + if (binit == 0) { + for (i = 0; i < NUMBER_OF_MLC_MODULE; i++) + __g_module_variables[i].pregister = NULL; + binit = 1; + } + return 1; +} + +u32 nx_mlc_get_physical_address(u32 module_index) +{ + const u32 physical_addr[] = PHY_BASEADDR_MLC_LIST; + + return physical_addr[module_index]; +} + +void nx_mlc_set_base_address(u32 module_index, void *base_address) +{ + __g_module_variables[module_index].pregister = + (struct nx_mlc_register_set *)base_address; +} + +void *nx_mlc_get_base_address(u32 module_index) +{ + return (void *)__g_module_variables[module_index].pregister; +} + +void nx_mlc_set_clock_pclk_mode(u32 module_index, enum nx_pclkmode mode) +{ + const u32 pclkmode_pos = 3; + u32 clkmode = 0; + + register u32 regvalue; + register struct nx_mlc_register_set *pregister; + + pregister = __g_module_variables[module_index].pregister; + switch (mode) { + case nx_pclkmode_dynamic: + clkmode = 0; + break; + case nx_pclkmode_always: + clkmode = 1; + break; + default: + break; + } + regvalue = pregister->mlcclkenb; + regvalue &= ~(1ul << pclkmode_pos); + regvalue |= (clkmode & 0x01) << pclkmode_pos; + + writel(regvalue, &pregister->mlcclkenb); +} + +enum nx_pclkmode nx_mlc_get_clock_pclk_mode(u32 module_index) +{ + const u32 pclkmode_pos = 3; + + if (__g_module_variables[module_index].pregister->mlcclkenb & + (1ul << pclkmode_pos)) { + return nx_pclkmode_always; + } + return nx_pclkmode_dynamic; +} + +void nx_mlc_set_clock_bclk_mode(u32 module_index, enum nx_bclkmode mode) +{ + register u32 regvalue; + register struct nx_mlc_register_set *pregister; + u32 clkmode = 0; + + pregister = __g_module_variables[module_index].pregister; + switch (mode) { + case nx_bclkmode_disable: + clkmode = 0; + break; + case nx_bclkmode_dynamic: + clkmode = 2; + break; + case nx_bclkmode_always: + clkmode = 3; + break; + default: + break; + } + regvalue = pregister->mlcclkenb; + regvalue &= ~(0x3); + regvalue |= clkmode & 0x3; + + writel(regvalue, &pregister->mlcclkenb); +} + +enum nx_bclkmode nx_mlc_get_clock_bclk_mode(u32 module_index) +{ + const u32 bclkmode = 3ul << 0; + + switch (__g_module_variables[module_index].pregister->mlcclkenb & + bclkmode) { + case 0: + return nx_bclkmode_disable; + case 2: + return nx_bclkmode_dynamic; + case 3: + return nx_bclkmode_always; + } + return nx_bclkmode_disable; +} + +void nx_mlc_set_top_power_mode(u32 module_index, int bpower) +{ + const u32 pixelbuffer_pwd_pos = 11; + const u32 pixelbuffer_pwd_mask = 1ul << pixelbuffer_pwd_pos; + const u32 dittyflag_mask = 1ul << 3; + register struct nx_mlc_register_set *pregister; + register u32 regvalue; + + pregister = __g_module_variables[module_index].pregister; + regvalue = pregister->mlccontrolt; + regvalue &= ~(pixelbuffer_pwd_mask | dittyflag_mask); + regvalue |= (bpower << pixelbuffer_pwd_pos); + + writel(regvalue, &pregister->mlccontrolt); +} + +int nx_mlc_get_top_power_mode(u32 module_index) +{ + const u32 pixelbuffer_pwd_pos = 11; + const u32 pixelbuffer_pwd_mask = 1ul << pixelbuffer_pwd_pos; + + return (int)((__g_module_variables[module_index].pregister->mlccontrolt + & pixelbuffer_pwd_mask) >> + pixelbuffer_pwd_pos); +} + +void nx_mlc_set_top_sleep_mode(u32 module_index, int bsleep) +{ + const u32 pixelbuffer_sld_pos = 10; + const u32 pixelbuffer_sld_mask = 1ul << pixelbuffer_sld_pos; + const u32 dittyflag_mask = 1ul << 3; + register struct nx_mlc_register_set *pregister; + register u32 regvalue; + + bsleep = (int)((u32)bsleep ^ 1); + pregister = __g_module_variables[module_index].pregister; + regvalue = pregister->mlccontrolt; + regvalue &= ~(pixelbuffer_sld_mask | dittyflag_mask); + regvalue |= (bsleep << pixelbuffer_sld_pos); + + writel(regvalue, &pregister->mlccontrolt); +} + +int nx_mlc_get_top_sleep_mode(u32 module_index) +{ + const u32 pixelbuffer_sld_pos = 11; + const u32 pixelbuffer_sld_mask = 1ul << pixelbuffer_sld_pos; + + return (int)(((__g_module_variables[module_index].pregister->mlccontrolt + & pixelbuffer_sld_mask) >> + pixelbuffer_sld_pos) ^ 0x01); +} + +void nx_mlc_set_top_dirty_flag(u32 module_index) +{ + const u32 dirtyflag = 1ul << 3; + register struct nx_mlc_register_set *pregister; + register u32 regvalue; + + pregister = __g_module_variables[module_index].pregister; + regvalue = pregister->mlccontrolt; + regvalue |= dirtyflag; + + writel(regvalue, &pregister->mlccontrolt); +} + +int nx_mlc_get_top_dirty_flag(u32 module_index) +{ + const u32 dirtyflag_pos = 3; + const u32 dirtyflag_mask = 1ul << dirtyflag_pos; + + return (int)((readl(&__g_module_variables[module_index] + .pregister->mlccontrolt) & + dirtyflag_mask) >> dirtyflag_pos); +} + +void nx_mlc_set_mlc_enable(u32 module_index, int benb) +{ + const u32 mlcenb_pos = 1; + const u32 mlcenb_mask = 1ul << mlcenb_pos; + const u32 dirtyflag_pos = 3; + const u32 dirtyflag_mask = 1ul << dirtyflag_pos; + register u32 regvalue; + register struct nx_mlc_register_set *pregister; + + pregister = __g_module_variables[module_index].pregister; + regvalue = pregister->mlccontrolt; + regvalue &= ~(mlcenb_mask | dirtyflag_mask); + regvalue |= (benb << mlcenb_pos); + + writel(regvalue, &pregister->mlccontrolt); +} + +int nx_mlc_get_mlc_enable(u32 module_index) +{ + const u32 mlcenb_pos = 1; + const u32 mlcenb_mask = 1ul << mlcenb_pos; + + return (int)((__g_module_variables[module_index].pregister->mlccontrolt + & mlcenb_mask) >> mlcenb_pos); +} + +void nx_mlc_set_field_enable(u32 module_index, int benb) +{ + const u32 fieldenb_pos = 0; + const u32 fieldenb_mask = 1ul << fieldenb_pos; + const u32 dirtyflag_pos = 3; + const u32 dirtyflag_mask = 1ul << dirtyflag_pos; + register u32 regvalue; + register struct nx_mlc_register_set *pregister; + + pregister = __g_module_variables[module_index].pregister; + regvalue = pregister->mlccontrolt; + regvalue &= ~(fieldenb_mask | dirtyflag_mask); + regvalue |= (benb << fieldenb_pos); + + writel(regvalue, &pregister->mlccontrolt); +} + +int nx_mlc_get_field_enable(u32 module_index) +{ + const u32 fieldenb_pos = 0; + const u32 fieldenb_mask = 1ul << fieldenb_pos; + + return (int)(__g_module_variables[module_index].pregister->mlccontrolt & + fieldenb_mask); +} + +void nx_mlc_set_layer_priority(u32 module_index, enum nx_mlc_priority priority) +{ + const u32 priority_pos = 8; + const u32 priority_mask = 0x03 << priority_pos; + const u32 dirtyflag_pos = 3; + const u32 dirtyflag_mask = 1ul << dirtyflag_pos; + register struct nx_mlc_register_set *pregister; + register u32 regvalue; + + pregister = __g_module_variables[module_index].pregister; + regvalue = pregister->mlccontrolt; + regvalue &= ~(priority_mask | dirtyflag_mask); + regvalue |= (priority << priority_pos); + + writel(regvalue, &pregister->mlccontrolt); +} + +void nx_mlc_set_screen_size(u32 module_index, u32 width, u32 height) +{ + register struct nx_mlc_register_set *pregister; + register u32 regvalue; + + pregister = __g_module_variables[module_index].pregister; + regvalue = ((height - 1) << 16) | (width - 1); + + writel(regvalue, &pregister->mlcscreensize); +} + +void nx_mlc_get_screen_size(u32 module_index, u32 *pwidth, u32 *pheight) +{ + register struct nx_mlc_register_set *pregister; + + pregister = __g_module_variables[module_index].pregister; + + if (pwidth) + *pwidth = (pregister->mlcscreensize & 0x0fff) + 1; + + if (pheight) + *pheight = ((pregister->mlcscreensize >> 16) & 0x0fff) + 1; +} + +void nx_mlc_set_background(u32 module_index, u32 color) +{ + register struct nx_mlc_register_set *pregister; + + pregister = __g_module_variables[module_index].pregister; + writel(color, &pregister->mlcbgcolor); +} + +void nx_mlc_set_dirty_flag(u32 module_index, u32 layer) +{ + register struct nx_mlc_register_set *pregister; + register u32 regvalue; + const u32 dirtyflg_mask = 1ul << 4; + + pregister = __g_module_variables[module_index].pregister; + if (layer == 0 || layer == 1) { + regvalue = pregister->mlcrgblayer[layer].mlccontrol; + regvalue |= dirtyflg_mask; + + writel(regvalue, &pregister->mlcrgblayer[layer].mlccontrol); + } else if (layer == 3) { + regvalue = pregister->mlcvideolayer.mlccontrol; + regvalue |= dirtyflg_mask; + + writel(regvalue, &pregister->mlcvideolayer.mlccontrol); + } +} + +int nx_mlc_get_dirty_flag(u32 module_index, u32 layer) +{ + const u32 dirtyflg_pos = 4; + const u32 dirtyflg_mask = 1ul << dirtyflg_pos; + + if (layer == 0 || layer == 1) { + return (int)((__g_module_variables[module_index] + .pregister->mlcrgblayer[layer] + .mlccontrol & dirtyflg_mask) >> dirtyflg_pos); + } else if (layer == 2) { + return (int)((__g_module_variables[module_index] + .pregister->mlcrgblayer2.mlccontrol & + dirtyflg_mask) >> dirtyflg_pos); + } else if (layer == 3) { + return (int)((__g_module_variables[module_index] + .pregister->mlcvideolayer.mlccontrol & + dirtyflg_mask) >> dirtyflg_pos); + } + return 0; +} + +void nx_mlc_set_layer_enable(u32 module_index, u32 layer, int benb) +{ + const u32 layerenb_pos = 5; + const u32 layerenb_mask = 0x01 << layerenb_pos; + const u32 dirtyflag_pos = 4; + const u32 dirtyflag_mask = 1ul << dirtyflag_pos; + register u32 regvalue; + register struct nx_mlc_register_set *pregister; + + pregister = __g_module_variables[module_index].pregister; + if (layer == 0 || layer == 1) { + regvalue = pregister->mlcrgblayer[layer].mlccontrol; + regvalue &= ~(layerenb_mask | dirtyflag_mask); + regvalue |= (benb << layerenb_pos); + + writel(regvalue, &pregister->mlcrgblayer[layer].mlccontrol); + } else if (layer == 3) { + regvalue = pregister->mlcvideolayer.mlccontrol; + regvalue &= ~(layerenb_mask | dirtyflag_mask); + regvalue |= (benb << layerenb_pos); + + writel(regvalue, &pregister->mlcvideolayer.mlccontrol); + } +} + +int nx_mlc_get_layer_enable(u32 module_index, u32 layer) +{ + const u32 layerenb_pos = 5; + const u32 layerenb_mask = 0x01 << layerenb_pos; + + if (layer == 0 || layer == 1) { + return (int)((__g_module_variables[module_index] + .pregister->mlcrgblayer[layer] + .mlccontrol & layerenb_mask) >> layerenb_pos); + } else if (layer == 3) { + return (int)((__g_module_variables[module_index] + .pregister->mlcvideolayer.mlccontrol & + layerenb_mask) >> layerenb_pos); + } + return 0; +} + +void nx_mlc_set_lock_size(u32 module_index, u32 layer, u32 locksize) +{ + const u32 locksize_mask = 3ul << 12; + const u32 dirtyflag_pos = 4; + const u32 dirtyflag_mask = 1ul << dirtyflag_pos; + register struct nx_mlc_register_set *pregister; + register u32 regvalue; + + pregister = __g_module_variables[module_index].pregister; + locksize >>= 3; + if (layer == 0 || layer == 1) { + regvalue = pregister->mlcrgblayer[layer].mlccontrol; + regvalue &= ~(locksize_mask | dirtyflag_mask); + regvalue |= (locksize << 12); + + writel(regvalue, &pregister->mlcrgblayer[layer].mlccontrol); + } +} + +void nx_mlc_set_alpha_blending(u32 module_index, u32 layer, int benb, u32 alpha) +{ + const u32 blendenb_pos = 2; + const u32 blendenb_mask = 0x01 << blendenb_pos; + const u32 dirtyflag_pos = 4; + const u32 dirtyflag_mask = 1ul << dirtyflag_pos; + const u32 alpha_pos = 28; + const u32 alpha_mask = 0xf << alpha_pos; + register u32 regvalue; + register struct nx_mlc_register_set *pregister; + + pregister = __g_module_variables[module_index].pregister; + if (layer == 0 || layer == 1) { + regvalue = pregister->mlcrgblayer[layer].mlccontrol; + regvalue &= ~(blendenb_mask | dirtyflag_mask); + regvalue |= (benb << blendenb_pos); + + writel(regvalue, &pregister->mlcrgblayer[layer].mlccontrol); + regvalue = pregister->mlcrgblayer[layer].mlctpcolor; + regvalue &= ~alpha_mask; + regvalue |= alpha << alpha_pos; + + writel(regvalue, &pregister->mlcrgblayer[layer].mlctpcolor); + } else if (layer == 3) { + regvalue = pregister->mlcvideolayer.mlccontrol; + regvalue &= ~(blendenb_mask | dirtyflag_mask); + regvalue |= (benb << blendenb_pos); + + writel(regvalue, &pregister->mlcvideolayer.mlccontrol); + + writel(alpha << alpha_pos, + &pregister->mlcvideolayer.mlctpcolor); + } +} + +void nx_mlc_set_transparency(u32 module_index, u32 layer, int benb, u32 color) +{ + const u32 tpenb_pos = 0; + const u32 tpenb_mask = 0x01 << tpenb_pos; + const u32 dirtyflag_pos = 4; + const u32 dirtyflag_mask = 1ul << dirtyflag_pos; + const u32 tpcolor_pos = 0; + const u32 tpcolor_mask = ((1 << 24) - 1) << tpcolor_pos; + register u32 regvalue; + register struct nx_mlc_register_set *pregister; + + pregister = __g_module_variables[module_index].pregister; + if (layer == 0 || layer == 1) { + regvalue = pregister->mlcrgblayer[layer].mlccontrol; + regvalue &= ~(tpenb_mask | dirtyflag_mask); + regvalue |= (benb << tpenb_pos); + + writel(regvalue, &pregister->mlcrgblayer[layer].mlccontrol); + regvalue = pregister->mlcrgblayer[layer].mlctpcolor; + regvalue &= ~tpcolor_mask; + regvalue |= (color & tpcolor_mask); + + writel(regvalue, &pregister->mlcrgblayer[layer].mlctpcolor); + } +} + +void nx_mlc_set_color_inversion(u32 module_index, u32 layer, int benb, + u32 color) +{ + const u32 invenb_pos = 1; + const u32 invenb_mask = 0x01 << invenb_pos; + const u32 dirtyflag_pos = 4; + const u32 dirtyflag_mask = 1ul << dirtyflag_pos; + const u32 invcolor_pos = 0; + const u32 invcolor_mask = ((1 << 24) - 1) << invcolor_pos; + register u32 regvalue; + register struct nx_mlc_register_set *pregister; + + pregister = __g_module_variables[module_index].pregister; + if (layer == 0 || layer == 1) { + regvalue = pregister->mlcrgblayer[layer].mlccontrol; + regvalue &= ~(invenb_mask | dirtyflag_mask); + regvalue |= (benb << invenb_pos); + + writel(regvalue, &pregister->mlcrgblayer[layer].mlccontrol); + regvalue = pregister->mlcrgblayer[layer].mlcinvcolor; + regvalue &= ~invcolor_mask; + regvalue |= (color & invcolor_mask); + + writel(regvalue, &pregister->mlcrgblayer[layer].mlcinvcolor); + } +} + +u32 nx_mlc_get_extended_color(u32 module_index, u32 color, + enum nx_mlc_rgbfmt format) +{ + u32 rgb[3] = { + 0, + }; + u32 bw[3] = { + 0, + }; + u32 bp[3] = { + 0, + }; + u32 blank = 0; + u32 fill = 0; + u32 i = 0; + + switch (format) { + case nx_mlc_rgbfmt_r5g6b5: + bw[0] = 5; + bw[1] = 6; + bw[2] = 5; + bp[0] = 11; + bp[1] = 5; + bp[2] = 0; + break; + case nx_mlc_rgbfmt_b5g6r5: + bw[0] = 5; + bw[1] = 6; + bw[2] = 5; + bp[0] = 0; + bp[1] = 5; + bp[2] = 11; + break; + case nx_mlc_rgbfmt_x1r5g5b5: + case nx_mlc_rgbfmt_a1r5g5b5: + bw[0] = 5; + bw[1] = 5; + bw[2] = 5; + bp[0] = 10; + bp[1] = 5; + bp[2] = 0; + break; + case nx_mlc_rgbfmt_x1b5g5r5: + case nx_mlc_rgbfmt_a1b5g5r5: + bw[0] = 5; + bw[1] = 5; + bw[2] = 5; + bp[0] = 0; + bp[1] = 5; + bp[2] = 10; + break; + case nx_mlc_rgbfmt_x4r4g4b4: + case nx_mlc_rgbfmt_a4r4g4b4: + bw[0] = 4; + bw[1] = 4; + bw[2] = 4; + bp[0] = 8; + bp[1] = 4; + bp[2] = 0; + break; + case nx_mlc_rgbfmt_x4b4g4r4: + case nx_mlc_rgbfmt_a4b4g4r4: + bw[0] = 4; + bw[1] = 4; + bw[2] = 4; + bp[0] = 0; + bp[1] = 4; + bp[2] = 8; + break; + case nx_mlc_rgbfmt_x8r3g3b2: + case nx_mlc_rgbfmt_a8r3g3b2: + bw[0] = 3; + bw[1] = 3; + bw[2] = 2; + bp[0] = 5; + bp[1] = 2; + bp[2] = 0; + break; + case nx_mlc_rgbfmt_x8b3g3r2: + case nx_mlc_rgbfmt_a8b3g3r2: + bw[0] = 2; + bw[1] = 3; + bw[2] = 3; + bp[0] = 0; + bp[1] = 2; + bp[2] = 5; + break; + case nx_mlc_rgbfmt_r8g8b8: + case nx_mlc_rgbfmt_a8r8g8b8: + bw[0] = 8; + bw[1] = 8; + bw[2] = 8; + bp[0] = 16; + bp[1] = 8; + bp[2] = 0; + break; + case nx_mlc_rgbfmt_b8g8r8: + case nx_mlc_rgbfmt_a8b8g8r8: + bw[0] = 8; + bw[1] = 8; + bw[2] = 8; + bp[0] = 0; + bp[1] = 8; + bp[2] = 16; + break; + default: + break; + } + for (i = 0; i < 3; i++) { + rgb[i] = (color >> bp[i]) & ((u32)(1 << bw[i]) - 1); + fill = bw[i]; + blank = 8 - fill; + rgb[i] <<= blank; + while (blank > 0) { + rgb[i] |= (rgb[i] >> fill); + blank -= fill; + fill += fill; + } + } + + return (rgb[0] << 16) | (rgb[1] << 8) | (rgb[2] << 0); +} + +void nx_mlc_set_format_rgb(u32 module_index, u32 layer, + enum nx_mlc_rgbfmt format) +{ + const u32 dirtyflag_pos = 4; + const u32 dirtyflag_mask = 1ul << dirtyflag_pos; + const u32 format_mask = 0xffff0000ul; + register u32 regvalue; + register struct nx_mlc_register_set *pregister; + + pregister = __g_module_variables[module_index].pregister; + if (layer == 0 || layer == 1) { + regvalue = pregister->mlcrgblayer[layer].mlccontrol; + regvalue &= ~(format_mask | dirtyflag_mask); + regvalue |= (u32)format; + + writel(regvalue, &pregister->mlcrgblayer[layer].mlccontrol); + } +} + +void nx_mlc_set_format_yuv(u32 module_index, enum nx_mlc_yuvfmt format) +{ + const u32 format_mask = 0xffff0000ul; + register u32 temp; + register struct nx_mlc_register_set *pregister; + + pregister = __g_module_variables[module_index].pregister; + temp = pregister->mlcvideolayer.mlccontrol; + temp &= ~format_mask; + temp |= (u32)format; + + writel(temp, &pregister->mlcvideolayer.mlccontrol); +} + +void nx_mlc_set_position(u32 module_index, u32 layer, s32 sx, s32 sy, + s32 ex, s32 ey) +{ + register struct nx_mlc_register_set *pregister; + + pregister = __g_module_variables[module_index].pregister; + if (layer == 0 || layer == 1) { + writel((((u32)sx & 0xffful) << 16) | ((u32)ex & 0xffful), + &pregister->mlcrgblayer[layer].mlcleftright); + + writel((((u32)sy & 0xffful) << 16) | ((u32)ey & 0xffful), + &pregister->mlcrgblayer[layer].mlctopbottom); + } else if (layer == 2) { + writel((((u32)sx & 0xffful) << 16) | ((u32)ex & 0xffful), + &pregister->mlcrgblayer2.mlcleftright); + + writel((((u32)sy & 0xffful) << 16) | ((u32)ey & 0xffful), + &pregister->mlcrgblayer2.mlctopbottom); + } else if (layer == 3) { + writel((((u32)sx & 0xffful) << 16) | ((u32)ex & 0xffful), + &pregister->mlcvideolayer.mlcleftright); + + writel((((u32)sy & 0xffful) << 16) | ((u32)ey & 0xffful), + &pregister->mlcvideolayer.mlctopbottom); + } +} + +void nx_mlc_set_dither_enable_when_using_gamma(u32 module_index, int benable) +{ + const u32 ditherenb_bitpos = 0; + const u32 ditherenb_mask = 1 << ditherenb_bitpos; + register struct nx_mlc_register_set *pregister; + register u32 read_value; + + pregister = __g_module_variables[module_index].pregister; + read_value = pregister->mlcgammacont; + read_value &= ~ditherenb_mask; + read_value |= ((u32)benable << ditherenb_bitpos); + + writel(read_value, &pregister->mlcgammacont); +} + +int nx_mlc_get_dither_enable_when_using_gamma(u32 module_index) +{ + const u32 ditherenb_bitpos = 0; + const u32 ditherenb_mask = 1 << ditherenb_bitpos; + + return (int)(__g_module_variables[module_index].pregister->mlcgammacont + & ditherenb_mask); +} + +void nx_mlc_set_gamma_priority(u32 module_index, int bvideolayer) +{ + const u32 alphaselect_bitpos = 5; + const u32 alphaselect_mask = 1 << alphaselect_bitpos; + register struct nx_mlc_register_set *pregister; + register u32 read_value; + + pregister = __g_module_variables[module_index].pregister; + read_value = pregister->mlcgammacont; + read_value &= ~alphaselect_mask; + read_value |= ((u32)bvideolayer << alphaselect_bitpos); + + writel(read_value, &pregister->mlcgammacont); +} + +int nx_mlc_get_gamma_priority(u32 module_index) +{ + const u32 alphaselect_bitpos = 5; + const u32 alphaselect_mask = 1 << alphaselect_bitpos; + + return (int)((__g_module_variables[module_index].pregister->mlcgammacont + & alphaselect_mask) >> alphaselect_bitpos); +} + +void nx_mlc_set_rgblayer_invalid_position(u32 module_index, u32 layer, + u32 region, s32 sx, s32 sy, + s32 ex, s32 ey, int benb) +{ + const u32 invalidenb_pos = 28; + register struct nx_mlc_register_set *pregister; + + pregister = __g_module_variables[module_index].pregister; + if (layer == 0 || layer == 1) { + if (region == 0) { + writel(((benb << invalidenb_pos) | + ((sx & 0x7ff) << 16) | (ex & 0x7ff)), + &pregister->mlcrgblayer[layer] + .mlcinvalidleftright0); + + writel((((sy & 0x7ff) << 16) | (ey & 0x7ff)), + &pregister->mlcrgblayer[layer] + .mlcinvalidtopbottom0); + } else { + writel(((benb << invalidenb_pos) | + ((sx & 0x7ff) << 16) | (ex & 0x7ff)), + &pregister->mlcrgblayer[layer] + .mlcinvalidleftright1); + + writel((((sy & 0x7ff) << 16) | (ey & 0x7ff)), + &pregister->mlcrgblayer[layer] + .mlcinvalidtopbottom1); + } + } +} + +void nx_mlc_set_rgblayer_stride(u32 module_index, u32 layer, s32 hstride, + s32 vstride) +{ + register struct nx_mlc_register_set *pregister; + + pregister = __g_module_variables[module_index].pregister; + if (layer == 0 || layer == 1) { + writel(hstride, &pregister->mlcrgblayer[layer].mlchstride); + writel(vstride, &pregister->mlcrgblayer[layer].mlcvstride); + } else if (layer == 2) { + writel(hstride, &pregister->mlcrgblayer2.mlchstride); + writel(vstride, &pregister->mlcrgblayer2.mlcvstride); + } +} + +void nx_mlc_set_rgblayer_address(u32 module_index, u32 layer, u32 addr) +{ + register struct nx_mlc_register_set *pregister; + + pregister = __g_module_variables[module_index].pregister; + if (layer == 0 || layer == 1) + writel(addr, &pregister->mlcrgblayer[layer].mlcaddress); + else if (layer == 2) + writel(addr, &pregister->mlcrgblayer2.mlcaddress); +} + +void nx_mlc_set_rgblayer_gama_table_power_mode(u32 module_index, int bred, + int bgreen, int bblue) +{ + const u32 bgammatable_pwd_bitpos = 11; + const u32 ggammatable_pwd_bitpos = 9; + const u32 rgammatable_pwd_bitpos = 3; + const u32 bgammatable_pwd_mask = (1 << bgammatable_pwd_bitpos); + const u32 ggammatable_pwd_mask = (1 << ggammatable_pwd_bitpos); + const u32 rgammatable_pwd_mask = (1 << rgammatable_pwd_bitpos); + register u32 read_value; + register struct nx_mlc_register_set *pregister; + + pregister = __g_module_variables[module_index].pregister; + read_value = pregister->mlcgammacont; + read_value &= ~(bgammatable_pwd_mask | ggammatable_pwd_mask | + rgammatable_pwd_mask); + read_value |= (((u32)bred << rgammatable_pwd_bitpos) | + ((u32)bgreen << ggammatable_pwd_bitpos) | + ((u32)bblue << bgammatable_pwd_bitpos)); + + writel(read_value, &pregister->mlcgammacont); +} + +void nx_mlc_get_rgblayer_gama_table_power_mode(u32 module_index, int *pbred, + int *pbgreen, int *pbblue) +{ + const u32 bgammatable_pwd_bitpos = 11; + const u32 ggammatable_pwd_bitpos = 9; + const u32 rgammatable_pwd_bitpos = 3; + const u32 bgammatable_pwd_mask = (1 << bgammatable_pwd_bitpos); + const u32 ggammatable_pwd_mask = (1 << ggammatable_pwd_bitpos); + const u32 rgammatable_pwd_mask = (1 << rgammatable_pwd_bitpos); + register u32 read_value; + register struct nx_mlc_register_set *pregister; + + pregister = __g_module_variables[module_index].pregister; + read_value = pregister->mlcgammacont; + if (pbred) + *pbred = (read_value & rgammatable_pwd_mask) ? 1 : 0; + + if (pbgreen) + *pbgreen = (read_value & ggammatable_pwd_mask) ? 1 : 0; + + if (pbblue) + *pbblue = (read_value & bgammatable_pwd_mask) ? 1 : 0; +} + +void nx_mlc_set_rgblayer_gama_table_sleep_mode(u32 module_index, int bred, + int bgreen, int bblue) +{ + const u32 bgammatable_sld_bitpos = 10; + const u32 ggammatable_sld_bitpos = 8; + const u32 rgammatable_sld_bitpos = 2; + const u32 bgammatable_sld_mask = (1 << bgammatable_sld_bitpos); + const u32 ggammatable_sld_mask = (1 << ggammatable_sld_bitpos); + const u32 rgammatable_sld_mask = (1 << rgammatable_sld_bitpos); + register u32 read_value; + register struct nx_mlc_register_set *pregister; + + pregister = __g_module_variables[module_index].pregister; + read_value = pregister->mlcgammacont; + if (bred) + read_value &= ~rgammatable_sld_mask; + else + read_value |= rgammatable_sld_mask; + + if (bgreen) + read_value &= ~ggammatable_sld_mask; + else + read_value |= ggammatable_sld_mask; + + if (bblue) + read_value &= ~bgammatable_sld_mask; + else + read_value |= bgammatable_sld_mask; + + writel(read_value, &pregister->mlcgammacont); +} + +void nx_mlc_get_rgblayer_gama_table_sleep_mode(u32 module_index, int *pbred, + int *pbgreen, int *pbblue) +{ + const u32 bgammatable_sld_bitpos = 10; + const u32 ggammatable_sld_bitpos = 8; + const u32 rgammatable_sld_bitpos = 2; + const u32 bgammatable_sld_mask = (1 << bgammatable_sld_bitpos); + const u32 ggammatable_sld_mask = (1 << ggammatable_sld_bitpos); + const u32 rgammatable_sld_mask = (1 << rgammatable_sld_bitpos); + register u32 read_value; + register struct nx_mlc_register_set *pregister; + + pregister = __g_module_variables[module_index].pregister; + read_value = pregister->mlcgammacont; + + if (pbred) + *pbred = (read_value & rgammatable_sld_mask) ? 0 : 1; + + if (pbgreen) + *pbgreen = (read_value & ggammatable_sld_mask) ? 0 : 1; + + if (pbblue) + *pbblue = (read_value & bgammatable_sld_mask) ? 0 : 1; +} + +void nx_mlc_set_rgblayer_rgamma_table(u32 module_index, u32 dwaddress, + u32 dwdata) +{ + register struct nx_mlc_register_set *pregister; + const u32 tableaddr_bitpos = 24; + + pregister = __g_module_variables[module_index].pregister; + writel(((dwaddress << tableaddr_bitpos) | dwdata), + &pregister->mlcrgammatablewrite); +} + +void nx_mlc_set_rgblayer_ggamma_table(u32 module_index, u32 dwaddress, + u32 dwdata) +{ + register struct nx_mlc_register_set *pregister; + const u32 tableaddr_bitpos = 24; + + pregister = __g_module_variables[module_index].pregister; + writel(((dwaddress << tableaddr_bitpos) | dwdata), + &pregister->mlcggammatablewrite); +} + +void nx_mlc_set_rgblayer_bgamma_table(u32 module_index, u32 dwaddress, + u32 dwdata) +{ + register struct nx_mlc_register_set *pregister; + const u32 tableaddr_bitpos = 24; + + pregister = __g_module_variables[module_index].pregister; + writel(((dwaddress << tableaddr_bitpos) | dwdata), + &pregister->mlcbgammatablewrite); +} + +void nx_mlc_set_rgblayer_gamma_enable(u32 module_index, int benable) +{ + const u32 rgbgammaemb_bitpos = 1; + const u32 rgbgammaemb_mask = 1 << rgbgammaemb_bitpos; + register u32 read_value; + register struct nx_mlc_register_set *pregister; + + pregister = __g_module_variables[module_index].pregister; + read_value = pregister->mlcgammacont; + read_value &= ~rgbgammaemb_mask; + read_value |= (u32)benable << rgbgammaemb_bitpos; + + writel(read_value, &pregister->mlcgammacont); +} + +int nx_mlc_get_rgblayer_gamma_enable(u32 module_index) +{ + const u32 rgbgammaemb_bitpos = 1; + const u32 rgbgammaemb_mask = 1 << rgbgammaemb_bitpos; + + return (int)((__g_module_variables[module_index].pregister->mlcgammacont + & rgbgammaemb_mask) >> rgbgammaemb_bitpos); +} + +void nx_mlc_set_video_layer_stride(u32 module_index, s32 lu_stride, + s32 cb_stride, s32 cr_stride) +{ + register struct nx_mlc_register_set *pregister; + + pregister = __g_module_variables[module_index].pregister; + + writel(lu_stride, &pregister->mlcvideolayer.mlcvstride); + writel(cb_stride, &pregister->mlcvideolayer.mlcvstridecb); + writel(cr_stride, &pregister->mlcvideolayer.mlcvstridecr); +} + +void nx_mlc_set_video_layer_address(u32 module_index, u32 lu_addr, u32 cb_addr, + u32 cr_addr) +{ + register struct nx_mlc_register_set *pregister; + + pregister = __g_module_variables[module_index].pregister; + writel(lu_addr, &pregister->mlcvideolayer.mlcaddress); + writel(cb_addr, &pregister->mlcvideolayer.mlcaddresscb); + writel(cr_addr, &pregister->mlcvideolayer.mlcaddresscr); +} + +void nx_mlc_set_video_layer_address_yuyv(u32 module_index, u32 addr, + s32 stride) +{ + register struct nx_mlc_register_set *pregister; + + pregister = __g_module_variables[module_index].pregister; + writel(addr, &pregister->mlcvideolayer.mlcaddress); + writel(stride, &pregister->mlcvideolayer.mlcvstride); +} + +void nx_mlc_set_video_layer_scale_factor(u32 module_index, u32 hscale, + u32 vscale, int bhlumaenb, + int bhchromaenb, int bvlumaenb, + int bvchromaenb) +{ + const u32 filter_luma_pos = 28; + const u32 filter_choma_pos = 29; + const u32 scale_mask = ((1 << 23) - 1); + register struct nx_mlc_register_set *pregister; + + pregister = __g_module_variables[module_index].pregister; + + writel(((bhlumaenb << filter_luma_pos) | + (bhchromaenb << filter_choma_pos) | (hscale & scale_mask)), + &pregister->mlcvideolayer.mlchscale); + + writel(((bvlumaenb << filter_luma_pos) | + (bvchromaenb << filter_choma_pos) | (vscale & scale_mask)), + &pregister->mlcvideolayer.mlcvscale); +} + +void nx_mlc_set_video_layer_scale_filter(u32 module_index, int bhlumaenb, + int bhchromaenb, int bvlumaenb, + int bvchromaenb) +{ + const u32 filter_luma_pos = 28; + const u32 filter_choma_pos = 29; + const u32 scale_mask = ((1 << 23) - 1); + register struct nx_mlc_register_set *pregister; + register u32 read_value; + + pregister = __g_module_variables[module_index].pregister; + read_value = pregister->mlcvideolayer.mlchscale; + read_value &= scale_mask; + read_value |= + (bhlumaenb << filter_luma_pos) | (bhchromaenb << filter_choma_pos); + + writel(read_value, &pregister->mlcvideolayer.mlchscale); + read_value = pregister->mlcvideolayer.mlcvscale; + read_value &= scale_mask; + read_value |= + (bvlumaenb << filter_luma_pos) | (bvchromaenb << filter_choma_pos); + + writel(read_value, &pregister->mlcvideolayer.mlcvscale); +} + +void nx_mlc_get_video_layer_scale_filter(u32 module_index, int *bhlumaenb, + int *bhchromaenb, int *bvlumaenb, + int *bvchromaenb) +{ + const u32 filter_luma_pos = 28; + const u32 filter_choma_pos = 29; + const u32 filter_mask = 1ul; + register struct nx_mlc_register_set *pregister; + register u32 read_value; + + pregister = __g_module_variables[module_index].pregister; + read_value = pregister->mlcvideolayer.mlchscale; + *bhlumaenb = (read_value >> filter_luma_pos) & filter_mask; + *bhchromaenb = (read_value >> filter_choma_pos) & filter_mask; + read_value = pregister->mlcvideolayer.mlcvscale; + *bvlumaenb = (read_value >> filter_luma_pos) & filter_mask; + *bvchromaenb = (read_value >> filter_choma_pos) & filter_mask; +} + +void nx_mlc_set_video_layer_scale(u32 module_index, u32 sw, u32 sh, u32 dw, + u32 dh, int bhlumaenb, int bhchromaenb, + int bvlumaenb, int bvchromaenb) +{ + const u32 filter_luma_pos = 28; + const u32 filter_choma_pos = 29; + const u32 scale_mask = ((1 << 23) - 1); + register u32 hscale, vscale, cal_sh; + register struct nx_mlc_register_set *pregister; + + pregister = __g_module_variables[module_index].pregister; + + if ((bhlumaenb || bhchromaenb) && dw > sw) { + sw--; + dw--; + } + hscale = (sw << 11) / dw; + + if ((bvlumaenb || bvchromaenb) && dh > sh) { + sh--; + dh--; + vscale = (sh << 11) / dh; + + cal_sh = ((vscale * dh) >> 11); + if (sh <= cal_sh) + vscale--; + + } else { + vscale = (sh << 11) / dh; + } + + writel(((bhlumaenb << filter_luma_pos) | + (bhchromaenb << filter_choma_pos) | (hscale & scale_mask)), + &pregister->mlcvideolayer.mlchscale); + + writel(((bvlumaenb << filter_luma_pos) | + (bvchromaenb << filter_choma_pos) | (vscale & scale_mask)), + &pregister->mlcvideolayer.mlcvscale); +} + +void nx_mlc_set_video_layer_luma_enhance(u32 module_index, u32 contrast, + s32 brightness) +{ + register struct nx_mlc_register_set *pregister; + + pregister = __g_module_variables[module_index].pregister; + + writel((((u32)brightness & 0xfful) << 8) | contrast, + &pregister->mlcvideolayer.mlcluenh); +} + +void nx_mlc_set_video_layer_chroma_enhance(u32 module_index, u32 quadrant, + s32 cb_a, s32 cb_b, + s32 cr_a, s32 cr_b) +{ + register struct nx_mlc_register_set *pregister; + register u32 temp; + + pregister = __g_module_variables[module_index].pregister; + temp = (((u32)cr_b & 0xfful) << 24) | (((u32)cr_a & 0xfful) << 16) | + (((u32)cb_b & 0xfful) << 8) | (((u32)cb_a & 0xfful) << 0); + if (quadrant > 0) { + writel(temp, &pregister->mlcvideolayer.mlcchenh[quadrant - 1]); + } else { + writel(temp, &pregister->mlcvideolayer.mlcchenh[0]); + writel(temp, &pregister->mlcvideolayer.mlcchenh[1]); + writel(temp, &pregister->mlcvideolayer.mlcchenh[2]); + writel(temp, &pregister->mlcvideolayer.mlcchenh[3]); + } +} + +void nx_mlc_set_video_layer_line_buffer_power_mode(u32 module_index, + int benable) +{ + const u32 linebuff_pwd_pos = 15; + const u32 linebuff_pwd_mask = 1ul << linebuff_pwd_pos; + const u32 dirtyflag_mask = 1ul << 4; + register u32 regvalue; + register struct nx_mlc_register_set *pregister; + + pregister = __g_module_variables[module_index].pregister; + regvalue = pregister->mlcvideolayer.mlccontrol; + regvalue &= ~(linebuff_pwd_mask | dirtyflag_mask); + regvalue |= ((u32)benable << linebuff_pwd_pos); + + writel(regvalue, &pregister->mlcvideolayer.mlccontrol); +} + +int nx_mlc_get_video_layer_line_buffer_power_mode(u32 module_index) +{ + const u32 linebuff_pwd_pos = 15; + const u32 linebuff_pwd_mask = 1ul << linebuff_pwd_pos; + + return (int)((__g_module_variables[module_index] + .pregister->mlcvideolayer.mlccontrol & + linebuff_pwd_mask) >> linebuff_pwd_pos); +} + +void nx_mlc_set_video_layer_line_buffer_sleep_mode(u32 module_index, + int benable) +{ + const u32 linebuff_slmd_pos = 14; + const u32 linebuff_slmd_mask = 1ul << linebuff_slmd_pos; + const u32 dirtyflag_mask = 1ul << 4; + register u32 regvalue; + register struct nx_mlc_register_set *pregister; + + benable = (int)((u32)benable ^ 1); + pregister = __g_module_variables[module_index].pregister; + regvalue = pregister->mlcvideolayer.mlccontrol; + regvalue &= ~(linebuff_slmd_mask | dirtyflag_mask); + regvalue |= (benable << linebuff_slmd_pos); + + writel(regvalue, &pregister->mlcvideolayer.mlccontrol); +} + +int nx_mlc_get_video_layer_line_buffer_sleep_mode(u32 module_index) +{ + const u32 linebuff_slmd_pos = 14; + const u32 linebuff_slmd_mask = 1ul << linebuff_slmd_pos; + register struct nx_mlc_register_set *pregister; + + pregister = __g_module_variables[module_index].pregister; + if (linebuff_slmd_mask & pregister->mlcvideolayer.mlccontrol) + return 0; + else + return 1; +} + +void nx_mlc_set_video_layer_gama_table_power_mode(u32 module_index, int by, + int bu, int bv) +{ + const u32 vgammatable_pwd_bitpos = 17; + const u32 ugammatable_pwd_bitpos = 15; + const u32 ygammatable_pwd_bitpos = 13; + const u32 vgammatable_pwd_mask = (1 << vgammatable_pwd_bitpos); + const u32 ugammatable_pwd_mask = (1 << ugammatable_pwd_bitpos); + const u32 ygammatable_pwd_mask = (1 << ygammatable_pwd_bitpos); + register u32 read_value; + register struct nx_mlc_register_set *pregister; + + pregister = __g_module_variables[module_index].pregister; + read_value = pregister->mlcgammacont; + read_value &= ~(ygammatable_pwd_mask | ugammatable_pwd_mask | + vgammatable_pwd_mask); + read_value |= (((u32)by << ygammatable_pwd_bitpos) | + ((u32)bu << ugammatable_pwd_bitpos) | + ((u32)bv << vgammatable_pwd_bitpos)); + + writel(read_value, &pregister->mlcgammacont); +} + +void nx_mlc_get_video_layer_gama_table_power_mode(u32 module_index, int *pby, + int *pbu, int *pbv) +{ + const u32 vgammatable_pwd_bitpos = 17; + const u32 ugammatable_pwd_bitpos = 15; + const u32 ygammatable_pwd_bitpos = 13; + const u32 vgammatable_pwd_mask = (1 << vgammatable_pwd_bitpos); + const u32 ugammatable_pwd_mask = (1 << ugammatable_pwd_bitpos); + const u32 ygammatable_pwd_mask = (1 << ygammatable_pwd_bitpos); + register u32 read_value; + register struct nx_mlc_register_set *pregister; + + pregister = __g_module_variables[module_index].pregister; + read_value = pregister->mlcgammacont; + if (pby) + *pby = (read_value & ygammatable_pwd_mask) ? 1 : 0; + + if (pbu) + *pbu = (read_value & ugammatable_pwd_mask) ? 1 : 0; + + if (pbv) + *pbv = (read_value & vgammatable_pwd_mask) ? 1 : 0; +} + +void nx_mlc_set_video_layer_gama_table_sleep_mode(u32 module_index, int by, + int bu, int bv) +{ + const u32 vgammatable_sld_bitpos = 16; + const u32 ugammatable_sld_bitpos = 14; + const u32 ygammatable_sld_bitpos = 12; + const u32 vgammatable_sld_mask = (1 << vgammatable_sld_bitpos); + const u32 ugammatable_sld_mask = (1 << ugammatable_sld_bitpos); + const u32 ygammatable_sld_mask = (1 << ygammatable_sld_bitpos); + register u32 read_value; + register struct nx_mlc_register_set *pregister; + + pregister = __g_module_variables[module_index].pregister; + read_value = pregister->mlcgammacont; + if (by) + read_value &= ~ygammatable_sld_mask; + else + read_value |= ygammatable_sld_mask; + + if (bu) + read_value &= ~ugammatable_sld_mask; + else + read_value |= ugammatable_sld_mask; + + if (bv) + read_value &= ~vgammatable_sld_mask; + else + read_value |= vgammatable_sld_mask; + + writel(read_value, &pregister->mlcgammacont); +} + +void nx_mlc_get_video_layer_gama_table_sleep_mode(u32 module_index, int *pby, + int *pbu, int *pbv) +{ + const u32 vgammatable_sld_bitpos = 16; + const u32 ugammatable_sld_bitpos = 14; + const u32 ygammatable_sld_bitpos = 12; + const u32 vgammatable_sld_mask = (1 << vgammatable_sld_bitpos); + const u32 ugammatable_sld_mask = (1 << ugammatable_sld_bitpos); + const u32 ygammatable_sld_mask = (1 << ygammatable_sld_bitpos); + register u32 read_value; + register struct nx_mlc_register_set *pregister; + + pregister = __g_module_variables[module_index].pregister; + read_value = pregister->mlcgammacont; + + if (pby) + *pby = (read_value & vgammatable_sld_mask) ? 0 : 1; + + if (pbu) + *pbu = (read_value & ugammatable_sld_mask) ? 0 : 1; + + if (pbv) + *pbv = (read_value & ygammatable_sld_mask) ? 0 : 1; +} + +void nx_mlc_set_video_layer_gamma_enable(u32 module_index, int benable) +{ + const u32 yuvgammaemb_bitpos = 4; + const u32 yuvgammaemb_mask = 1 << yuvgammaemb_bitpos; + register u32 read_value; + register struct nx_mlc_register_set *pregister; + + pregister = __g_module_variables[module_index].pregister; + read_value = pregister->mlcgammacont; + read_value &= ~yuvgammaemb_mask; + read_value |= (u32)benable << yuvgammaemb_bitpos; + + writel(read_value, &pregister->mlcgammacont); +} + +int nx_mlc_get_video_layer_gamma_enable(u32 module_index) +{ + const u32 yuvgammaemb_bitpos = 4; + const u32 yuvgammaemb_mask = 1 << yuvgammaemb_bitpos; + + return (int)((__g_module_variables[module_index].pregister->mlcgammacont + & yuvgammaemb_mask) >> yuvgammaemb_bitpos); +} + +void nx_mlc_set_gamma_table_poweroff(u32 module_index, int enb) +{ + register struct nx_mlc_register_set *pregister; + u32 regvalue; + + pregister = __g_module_variables[module_index].pregister; + if (enb == 1) { + regvalue = pregister->mlcgammacont; + regvalue = regvalue & 0xf3; + writel(regvalue, &pregister->mlcgammacont); + } +} + +void nx_mlc_set_mlctop_control_parameter(u32 module_index, int field_enable, + int mlcenable, u8 priority, + enum g3daddrchangeallowed + g3daddr_change_allowed) +{ + register u32 mlctopcontrolreg; + register struct nx_mlc_register_set *pregister; + + pregister = __g_module_variables[module_index].pregister; + mlctopcontrolreg = (readl(&pregister->mlccontrolt)) & 0xfffffcfc; + mlctopcontrolreg = (u32)(mlctopcontrolreg | + ((priority << 8) | ((mlcenable == 1) << 1) | + (1 == + field_enable)) | (g3daddr_change_allowed << + 12)); + writel(mlctopcontrolreg, &pregister->mlccontrolt); +} + +void nx_mlc_set_rgb0layer_control_parameter(u32 module_index, int layer_enable, + int grp3denable, int tp_enable, + u32 transparency_color, + int inv_enable, u32 inverse_color, + int blend_enable, u8 alpha_value, + enum mlc_rgbfmt rbgformat, + enum locksizesel lock_size_select) +{ + u32 layer_format; + u32 control_enb; + u32 alpha_argument; + u32 lock_size = (u32)(lock_size_select & 0x3); + u32 rgb0controlreg; + u32 regvalue; + register struct nx_mlc_register_set *pregister; + + layer_format = nx_mlc_get_rgbformat(rbgformat); + pregister = __g_module_variables[module_index].pregister; + control_enb = + (u32)((grp3denable << 8) | (layer_enable << 5) | + (blend_enable << 2) | (inv_enable << 1) | tp_enable) & 0x127; + alpha_argument = (u32)(alpha_value & 0xf); + + rgb0controlreg = readl(&pregister->mlcrgblayer[0].mlccontrol) & 0x10; + regvalue = + (u32)(((layer_format << 16) | control_enb | (lock_size << 12)) | + rgb0controlreg); + writel(regvalue, &pregister->mlcrgblayer[0].mlccontrol); + + regvalue = (u32)((alpha_argument << 28) | transparency_color); + writel(regvalue, &pregister->mlcrgblayer[0].mlctpcolor); + regvalue = inverse_color; + writel(regvalue, &pregister->mlcrgblayer[0].mlcinvcolor); +} + +u32 nx_mlc_get_rgbformat(enum mlc_rgbfmt rbgformat) +{ + u32 rgbformatvalue; + const u32 format_table[] = { + 0x4432ul, 0x4342ul, 0x4211ul, 0x4120ul, 0x4003ul, 0x4554ul, + 0x3342ul, 0x2211ul, 0x1120ul, 0x1003ul, 0x4653ul, 0x4653ul, + 0x0653ul, 0x4ed3ul, 0x4f84ul, 0xc432ul, 0xc342ul, 0xc211ul, + 0xc120ul, 0xb342ul, 0xa211ul, 0x9120ul, 0xc653ul, 0xc653ul, + 0x8653ul, 0xced3ul, 0xcf84ul, 0x443aul + }; + + return rgbformatvalue = format_table[rbgformat]; +} + +void nx_mlc_set_rgb1layer_control_parameter(u32 module_index, int layer_enable, + int grp3denable, int tp_enable, + u32 transparency_color, + int inv_enable, u32 inverse_color, + int blend_enable, u8 alpha_value, + enum mlc_rgbfmt rbgformat, + enum locksizesel lock_size_select) +{ + u32 layer_format; + u32 control_enb; + u32 alpha_argument; + u32 lock_size = (u32)(lock_size_select & 0x3); + u32 rgb0controlreg; + u32 regvalue; + register struct nx_mlc_register_set *pregister; + + layer_format = nx_mlc_get_rgbformat(rbgformat); + pregister = __g_module_variables[module_index].pregister; + + rgb0controlreg = readl(&pregister->mlcrgblayer[1].mlccontrol) & 0x10; + control_enb = + (u32)((grp3denable << 8) | (layer_enable << 5) | + (blend_enable << 2) | (inv_enable << 1) | tp_enable) & 0x127; + alpha_argument = (u32)(alpha_value & 0xf); + regvalue = + (u32)(((layer_format << 16) | control_enb | (lock_size << 12)) | + rgb0controlreg); + writel(regvalue, &pregister->mlcrgblayer[1].mlccontrol); + regvalue = (u32)((alpha_argument << 28) | transparency_color); + writel(regvalue, &pregister->mlcrgblayer[1].mlctpcolor); + regvalue = inverse_color; + writel(regvalue, &pregister->mlcrgblayer[1].mlcinvcolor); +} + +void nx_mlc_set_rgb2layer_control_parameter(u32 module_index, int layer_enable, + int grp3denable, int tp_enable, + u32 transparency_color, + int inv_enable, u32 inverse_color, + int blend_enable, u8 alpha_value, + enum mlc_rgbfmt rbgformat, + enum locksizesel lock_size_select) +{ + u32 layer_format; + u32 control_enb; + u32 alpha_argument; + u32 lock_size = (u32)(lock_size_select & 0x3); + u32 rgb0controlreg; + u32 regvalue; + register struct nx_mlc_register_set *pregister; + + layer_format = nx_mlc_get_rgbformat(rbgformat); + pregister = __g_module_variables[module_index].pregister; + + rgb0controlreg = readl(&pregister->mlcrgblayer2.mlccontrol) & 0x10; + control_enb = + (u32)((grp3denable << 8) | (layer_enable << 5) | + (blend_enable << 2) | (inv_enable << 1) | tp_enable) & 0x127; + alpha_argument = (u32)(alpha_value & 0xf); + regvalue = + (u32)(((layer_format << 16) | control_enb | (lock_size << 12)) | + rgb0controlreg); + writel(regvalue, &pregister->mlcrgblayer2.mlccontrol); + regvalue = (u32)((alpha_argument << 28) | transparency_color); + writel(regvalue, &pregister->mlcrgblayer2.mlctpcolor); + regvalue = inverse_color; + writel(regvalue, &pregister->mlcrgblayer2.mlcinvcolor); +} + +void nx_mlc_set_video_layer_control_parameter(u32 module_index, + int layer_enable, int tp_enable, + u32 transparency_color, + int inv_enable, u32 inverse_color, + int blend_enable, u8 alpha_value, + enum nx_mlc_yuvfmt yuvformat) +{ + u32 control_enb; + u32 alpha_argument; + u32 regvalue; + register struct nx_mlc_register_set *pregister; + u32 video_control_reg; + + pregister = __g_module_variables[module_index].pregister; + + video_control_reg = readl(&pregister->mlcvideolayer.mlccontrol); + control_enb = + (u32)((yuvformat) | (layer_enable << 5) | (blend_enable << 2) | + (inv_enable << 1) | tp_enable) & 0x30027; + alpha_argument = (u32)(alpha_value & 0xf); + regvalue = (u32)(control_enb | video_control_reg); + writel(regvalue, &pregister->mlcvideolayer.mlccontrol); + regvalue = (u32)((alpha_argument << 28) | transparency_color); + writel(regvalue, &pregister->mlcvideolayer.mlctpcolor); + regvalue = (u32)((alpha_argument << 28) | transparency_color); + writel(regvalue, &pregister->mlcvideolayer.mlcinvcolor); +} + +void nx_mlc_set_srammode(u32 module_index, enum latyername layer_name, + enum srammode sram_mode) +{ + u32 control_reg_value; + register struct nx_mlc_register_set *pregister; + + pregister = __g_module_variables[module_index].pregister; + switch (layer_name) { + case topmlc: + control_reg_value = readl(&pregister->mlccontrolt); + writel((u32)(control_reg_value | (sram_mode << 10)), + &pregister->mlccontrolt); + control_reg_value = 0; + break; + case rgb0: + control_reg_value = + readl(&pregister->mlcrgblayer[0].mlccontrol); + writel((u32)(control_reg_value | (sram_mode << 14)), + &pregister->mlcrgblayer[0].mlccontrol); + control_reg_value = 0; + break; + case rgb1: + control_reg_value = + readl(&pregister->mlcrgblayer[1].mlccontrol); + writel((u32)(control_reg_value | (sram_mode << 14)), + &pregister->mlcrgblayer[1].mlccontrol); + control_reg_value = 0; + break; + case rgb2: + control_reg_value = readl(&pregister->mlcrgblayer2.mlccontrol); + writel((u32)(control_reg_value | (sram_mode << 14)), + &pregister->mlcrgblayer2.mlccontrol); + control_reg_value = 0; + break; + case video: + control_reg_value = readl(&pregister->mlcvideolayer.mlccontrol); + writel((u32)(control_reg_value | (sram_mode << 14)), + &pregister->mlcvideolayer.mlccontrol); + control_reg_value = 0; + break; + default: + break; + } +} + +void nx_mlc_set_layer_reg_finish(u32 module_index, enum latyername layer_name) +{ + u32 control_reg_value; + register struct nx_mlc_register_set *pregister; + + pregister = __g_module_variables[module_index].pregister; + + switch (layer_name) { + case topmlc: + control_reg_value = readl(&pregister->mlccontrolt); + writel((u32)(control_reg_value | (1ul << 3)), + &pregister->mlccontrolt); + control_reg_value = 0; + break; + case rgb0: + control_reg_value = + readl(&pregister->mlcrgblayer[0].mlccontrol); + writel((u32)(control_reg_value | (1ul << 4)), + &pregister->mlcrgblayer[0].mlccontrol); + control_reg_value = 0; + break; + case rgb1: + control_reg_value = + readl(&pregister->mlcrgblayer[1].mlccontrol); + writel((u32)(control_reg_value | (1ul << 4)), + &pregister->mlcrgblayer[1].mlccontrol); + control_reg_value = 0; + break; + case rgb2: + control_reg_value = readl(&pregister->mlcrgblayer2.mlccontrol); + writel((u32)(control_reg_value | (1ul << 4)), + &pregister->mlcrgblayer2.mlccontrol); + control_reg_value = 0; + break; + case video: + control_reg_value = readl(&pregister->mlcvideolayer.mlccontrol); + writel((u32)(control_reg_value | (1ul << 4)), + &pregister->mlcvideolayer.mlccontrol); + control_reg_value = 0; + break; + default: + break; + } +} + +void nx_mlc_set_video_layer_coordinate(u32 module_index, int vfilterenable, + int hfilterenable, int vfilterenable_c, + int hfilterenable_c, + u16 video_layer_with, + u16 video_layer_height, s16 left, + s16 right, s16 top, + s16 bottom) +{ + s32 source_width, source_height; + s32 destination_width; + s32 destination_height; + s32 hscale, vscale; + s32 hfilterenb, vfilterenb; + register struct nx_mlc_register_set *pregister; + + pregister = __g_module_variables[module_index].pregister; + writel((s32)(((left & 0x0fff) << 16) | (right & 0x0fff)), + &pregister->mlcvideolayer.mlcleftright); + writel((s32)(((top & 0x0fff) << 16) | (bottom & 0x0fff)), + &pregister->mlcvideolayer.mlctopbottom); + source_width = (s32)(video_layer_with - 1); + source_height = (s32)(video_layer_height - 1); + destination_width = (s32)(right - left); + destination_height = (s32)(bottom - top); + + hscale = + (s32)((source_width * (1ul << 11) + (destination_width / 2)) / + destination_width); + vscale = + (s32)((source_height * (1ul << 11) + + (destination_height / 2)) / destination_height); + + hfilterenb = (u32)(((hfilterenable_c << 29) | (hfilterenable) << 28)) & + 0x30000000; + vfilterenb = (u32)(((vfilterenable_c << 29) | (vfilterenable) << 28)) & + 0x30000000; + writel((u32)(hfilterenb | (hscale & 0x00ffffff)), + &pregister->mlcvideolayer.mlchscale); + writel((u32)(vfilterenb | (vscale & 0x00ffffff)), + &pregister->mlcvideolayer.mlcvscale); +} + +void nx_mlc_set_video_layer_filter_scale(u32 module_index, u32 hscale, + u32 vscale) +{ + register struct nx_mlc_register_set *pregister; + u32 mlchscale = 0; + u32 mlcvscale = 0; + + pregister = __g_module_variables[module_index].pregister; + mlchscale = readl(&pregister->mlcvideolayer.mlchscale) & (~0x00ffffff); + mlcvscale = readl(&pregister->mlcvideolayer.mlcvscale) & (~0x00ffffff); + + writel((u32)(mlchscale | (hscale & 0x00ffffff)), + &pregister->mlcvideolayer.mlchscale); + writel((u32)(mlcvscale | (vscale & 0x00ffffff)), + &pregister->mlcvideolayer.mlcvscale); +} + +void nx_mlc_set_gamma_control_parameter(u32 module_index, int rgbgammaenb, + int yuvgammaenb, int yuvalphaarray, + int dither_enb) +{ + u32 register_data; + register struct nx_mlc_register_set *pregister; + + pregister = __g_module_variables[module_index].pregister; + register_data = readl(&pregister->mlcgammacont); + register_data = (register_data & 0xf0c) | + ((yuvalphaarray << 5) | (yuvgammaenb << 4) | + (rgbgammaenb << 1) | (dither_enb << 0)); + writel(register_data, &pregister->mlcgammacont); +} + +void nx_mlc_set_layer_alpha256(u32 module_index, u32 layer, u32 alpha) +{ + u32 register_data; + register struct nx_mlc_register_set *pregister; + + if (alpha < 0) + alpha = 0; + if (alpha > 255) + alpha = 255; + + pregister = __g_module_variables[module_index].pregister; + if (layer == 0) { + register_data = + readl(&pregister->mlcrgblayer[0].mlctpcolor) & 0x00ffffff; + register_data = register_data | (alpha << 24); + writel(register_data, &pregister->mlcrgblayer[0].mlctpcolor); + } else if (layer == 1) { + register_data = + readl(&pregister->mlcrgblayer[1].mlctpcolor) & 0x00ffffff; + register_data = register_data | (alpha << 24); + writel(register_data, &pregister->mlcrgblayer[1].mlctpcolor); + } else if (layer == 2) { + register_data = + readl(&pregister->mlcrgblayer[1].mlctpcolor) & 0x00ffffff; + register_data = register_data | (alpha << 24); + writel(register_data, &pregister->mlcrgblayer2.mlctpcolor); + } else { + register_data = + readl(&pregister->mlcvideolayer.mlctpcolor) & 0x00ffffff; + register_data = register_data | (alpha << 24); + writel(register_data, &pregister->mlcvideolayer.mlctpcolor); + } +} + +int nx_mlc_is_under_flow(u32 module_index) +{ + const u32 underflow_pend_pos = 31; + const u32 underflow_pend_mask = 1ul << underflow_pend_pos; + + return (int)((__g_module_variables[module_index].pregister->mlccontrolt + & underflow_pend_mask) >> underflow_pend_pos); +} + +void nx_mlc_set_gamma_table(u32 module_index, int enb, + struct nx_mlc_gamma_table_parameter *p_gammatable) +{ + register struct nx_mlc_register_set *pregister; + u32 i, regval = 0; + + pregister = __g_module_variables[module_index].pregister; + if (enb == 1) { + regval = readl(&pregister->mlcgammacont); + + regval = (1 << 11) | (1 << 9) | (1 << 3); + writel(regval, &pregister->mlcgammacont); + + regval = regval | (1 << 10) | (1 << 8) | (1 << 2); + writel(regval, &pregister->mlcgammacont); + + for (i = 0; i < 256; i++) { + nx_mlc_set_rgblayer_rgamma_table(module_index, i, + p_gammatable->r_table[i]); + nx_mlc_set_rgblayer_ggamma_table(module_index, i, + p_gammatable->g_table[i]); + nx_mlc_set_rgblayer_bgamma_table(module_index, i, + p_gammatable->b_table[i]); + } + + regval = regval | (p_gammatable->alphaselect << 5) | + (p_gammatable->yuvgammaenb << 4 | + p_gammatable->allgammaenb << 4) | + (p_gammatable->rgbgammaenb << 1 | + p_gammatable->allgammaenb << 1) | + (p_gammatable->ditherenb << 1); + writel(regval, &pregister->mlcgammacont); + } else { + regval = regval & ~(1 << 10) & ~(1 << 8) & ~(1 << 2); + writel(regval, &pregister->mlcgammacont); + + regval = regval & ~(1 << 11) & ~(1 << 9) & ~(1 << 3); + writel(regval, &pregister->mlcgammacont); + } +} + +void nx_mlc_get_rgblayer_stride(u32 module_index, u32 layer, s32 *hstride, + s32 *vstride) +{ + unsigned int hs, vs; + register struct nx_mlc_register_set *pregister; + + pregister = __g_module_variables[module_index].pregister; + + hs = readl(&pregister->mlcrgblayer[layer].mlchstride); + vs = readl(&pregister->mlcrgblayer[layer].mlcvstride); + + if (hstride) + *(s32 *)hstride = hs; + + if (vstride) + *(s32 *)vstride = vs; +} + +void nx_mlc_get_rgblayer_address(u32 module_index, u32 layer, + u32 *phys_address) +{ + u32 pa; + register struct nx_mlc_register_set *pregister; + + pregister = __g_module_variables[module_index].pregister; + pa = readl(&pregister->mlcrgblayer[layer].mlcaddress); + + if (phys_address) + *(u32 *)phys_address = pa; +} + +void nx_mlc_get_position(u32 module_index, u32 layer, int *left, int *top, + int *right, int *bottom) +{ + int lr, tb; + register struct nx_mlc_register_set *pregister; + + pregister = __g_module_variables[module_index].pregister; + + lr = readl(&pregister->mlcrgblayer[layer].mlcleftright); + tb = readl(&pregister->mlcrgblayer[layer].mlctopbottom); + + if (left) + *(int *)left = ((lr >> 16) & 0xFFUL); + + if (top) + *(int *)top = ((tb >> 16) & 0xFFUL); + + if (right) + *(int *)right = ((lr >> 0) & 0xFFUL); + + if (bottom) + *(int *)bottom = ((tb >> 0) & 0xFFUL); +} + +void nx_mlc_get_video_layer_address_yuyv(u32 module_index, u32 *address, + u32 *stride) +{ + u32 a, s; + register struct nx_mlc_register_set *pregister; + + pregister = __g_module_variables[module_index].pregister; + a = readl(&pregister->mlcvideolayer.mlcaddress); + s = readl(&pregister->mlcvideolayer.mlcvstride); + + if (address) + *(u32 *)address = a; + + if (stride) + *(u32 *)stride = s; +} + +void nx_mlc_get_video_layer_address(u32 module_index, u32 *lu_address, + u32 *cb_address, u32 *cr_address) +{ + u32 lua, cba, cra; + register struct nx_mlc_register_set *pregister; + + pregister = __g_module_variables[module_index].pregister; + + lua = readl(&pregister->mlcvideolayer.mlcaddress); + cba = readl(&pregister->mlcvideolayer.mlcaddresscb); + cra = readl(&pregister->mlcvideolayer.mlcaddresscr); + + if (lu_address) + *(u32 *)lu_address = lua; + + if (cb_address) + *(u32 *)cb_address = cba; + + if (cr_address) + *(u32 *)cr_address = cra; +} + +void nx_mlc_get_video_layer_stride(u32 module_index, u32 *lu_stride, + u32 *cb_stride, u32 *cr_stride) +{ + u32 lus, cbs, crs; + register struct nx_mlc_register_set *pregister; + + pregister = __g_module_variables[module_index].pregister; + + lus = readl(&pregister->mlcvideolayer.mlcvstride); + cbs = readl(&pregister->mlcvideolayer.mlcvstridecb); + crs = readl(&pregister->mlcvideolayer.mlcvstridecr); + + if (lu_stride) + *(u32 *)lu_stride = lus; + + if (cb_stride) + *(u32 *)cb_stride = cbs; + + if (cr_stride) + *(u32 *)cr_stride = crs; +} + +void nx_mlc_get_video_position(u32 module_index, int *left, int *top, + int *right, int *bottom) +{ + int lr, tb; + register struct nx_mlc_register_set *pregister; + + pregister = __g_module_variables[module_index].pregister; + + lr = readl(&pregister->mlcvideolayer.mlcleftright); + tb = readl(&pregister->mlcvideolayer.mlctopbottom); + + if (left) + *(int *)left = ((lr >> 16) & 0xFFUL); + + if (top) + *(int *)top = ((tb >> 16) & 0xFFUL); + + if (right) + *(int *)right = ((lr >> 0) & 0xFFUL); + + if (bottom) + *(int *)bottom = ((tb >> 0) & 0xFFUL); +} diff --git a/drivers/video/nexell/soc/s5pxx18_soc_mlc.h b/drivers/video/nexell/soc/s5pxx18_soc_mlc.h new file mode 100644 index 0000000..77ceca6 --- /dev/null +++ b/drivers/video/nexell/soc/s5pxx18_soc_mlc.h @@ -0,0 +1,429 @@ +/* SPDX-License-Identifier: GPL-2.0+ + * + * Copyright (C) 2016 Nexell Co., Ltd. + * + * Author: junghyun, kim + */ + +#ifndef _S5PXX18_SOC_MLC_H_ +#define _S5PXX18_SOC_MLC_H_ + +#include "s5pxx18_soc_disptype.h" + +#define NUMBER_OF_MLC_MODULE 2 +#define PHY_BASEADDR_MLC0 0xC0102000 +#define PHY_BASEADDR_MLC1 0xC0102400 + +#define PHY_BASEADDR_MLC_LIST \ + { PHY_BASEADDR_MLC0, PHY_BASEADDR_MLC1 } + +struct nx_mlc_register_set { + u32 mlccontrolt; + u32 mlcscreensize; + u32 mlcbgcolor; + struct { + u32 mlcleftright; + u32 mlctopbottom; + u32 mlcinvalidleftright0; + u32 mlcinvalidtopbottom0; + u32 mlcinvalidleftright1; + u32 mlcinvalidtopbottom1; + u32 mlccontrol; + s32 mlchstride; + s32 mlcvstride; + u32 mlctpcolor; + u32 mlcinvcolor; + u32 mlcaddress; + u32 __reserved0; + } mlcrgblayer[2]; + struct { + u32 mlcleftright; + u32 mlctopbottom; + u32 mlccontrol; + u32 mlcvstride; + u32 mlctpcolor; + + u32 mlcinvcolor; + u32 mlcaddress; + u32 mlcaddresscb; + u32 mlcaddresscr; + s32 mlcvstridecb; + s32 mlcvstridecr; + u32 mlchscale; + u32 mlcvscale; + u32 mlcluenh; + u32 mlcchenh[4]; + } mlcvideolayer; + struct { + u32 mlcleftright; + u32 mlctopbottom; + u32 mlcinvalidleftright0; + u32 mlcinvalidtopbottom0; + u32 mlcinvalidleftright1; + u32 mlcinvalidtopbottom1; + u32 mlccontrol; + s32 mlchstride; + s32 mlcvstride; + u32 mlctpcolor; + u32 mlcinvcolor; + u32 mlcaddress; + } mlcrgblayer2; + u32 mlcpaletetable2; + u32 mlcgammacont; + u32 mlcrgammatablewrite; + u32 mlcggammatablewrite; + u32 mlcbgammatablewrite; + u32 yuvlayergammatable_red; + u32 yuvlayergammatable_green; + u32 yuvlayergammatable_blue; + + u32 dimctrl; + u32 dimlut0; + u32 dimlut1; + u32 dimbusyflag; + u32 dimprdarrr0; + u32 dimprdarrr1; + u32 dimram0rddata; + u32 dimram1rddata; + u32 __reserved2[(0x3c0 - 0x12c) / 4]; + u32 mlcclkenb; +}; + +enum nx_mlc_priority { + nx_mlc_priority_videofirst = 0ul, + nx_mlc_priority_videosecond = 1ul, + nx_mlc_priority_videothird = 2ul, + nx_mlc_priority_videofourth = 3ul +}; + +enum nx_mlc_rgbfmt { + nx_mlc_rgbfmt_r5g6b5 = 0x44320000ul, + nx_mlc_rgbfmt_b5g6r5 = 0xc4320000ul, + nx_mlc_rgbfmt_x1r5g5b5 = 0x43420000ul, + nx_mlc_rgbfmt_x1b5g5r5 = 0xc3420000ul, + nx_mlc_rgbfmt_x4r4g4b4 = 0x42110000ul, + nx_mlc_rgbfmt_x4b4g4r4 = 0xc2110000ul, + nx_mlc_rgbfmt_x8r3g3b2 = 0x41200000ul, + nx_mlc_rgbfmt_x8b3g3r2 = 0xc1200000ul, + nx_mlc_rgbfmt_a1r5g5b5 = 0x33420000ul, + nx_mlc_rgbfmt_a1b5g5r5 = 0xb3420000ul, + nx_mlc_rgbfmt_a4r4g4b4 = 0x22110000ul, + nx_mlc_rgbfmt_a4b4g4r4 = 0xa2110000ul, + nx_mlc_rgbfmt_a8r3g3b2 = 0x11200000ul, + nx_mlc_rgbfmt_a8b3g3r2 = 0x91200000ul, + nx_mlc_rgbfmt_r8g8b8 = 0x46530000ul, + nx_mlc_rgbfmt_b8g8r8 = 0xc6530000ul, + nx_mlc_rgbfmt_x8r8g8b8 = 0x46530000ul, + nx_mlc_rgbfmt_x8b8g8r8 = 0xc6530000ul, + nx_mlc_rgbfmt_a8r8g8b8 = 0x06530000ul, + nx_mlc_rgbfmt_a8b8g8r8 = 0x86530000ul +}; + +enum nx_mlc_yuvfmt { + nx_mlc_yuvfmt_420 = 0ul << 16, + nx_mlc_yuvfmt_422 = 1ul << 16, + nx_mlc_yuvfmt_444 = 3ul << 16, + nx_mlc_yuvfmt_yuyv = 2ul << 16, + nx_mlc_yuvfmt_422_cbcr = 4ul << 16, + nx_mlc_yuvfmt_420_cbcr = 5ul << 16, +}; + +#ifdef __arm +#pragma diag_default 66 +#endif + +int nx_mlc_initialize(void); +u32 nx_mlc_get_number_of_module(void); +u32 nx_mlc_get_physical_address(u32 module_index); +u32 nx_mlc_get_size_of_register_set(void); +void nx_mlc_set_base_address(u32 module_index, void *base_address); +void *nx_mlc_get_base_address(u32 module_index); +int nx_mlc_open_module(u32 module_index); +int nx_mlc_close_module(u32 module_index); +int nx_mlc_check_busy(u32 module_index); +int nx_mlc_can_power_down(u32 module_index); +void nx_mlc_set_clock_pclk_mode(u32 module_index, enum nx_pclkmode mode); +enum nx_pclkmode nx_mlc_get_clock_pclk_mode(u32 module_index); +void nx_mlc_set_clock_bclk_mode(u32 module_index, enum nx_bclkmode mode); +enum nx_bclkmode nx_mlc_get_clock_bclk_mode(u32 module_index); + +void nx_mlc_set_top_power_mode(u32 module_index, int bpower); +int nx_mlc_get_top_power_mode(u32 module_index); +void nx_mlc_set_top_sleep_mode(u32 module_index, int bsleep); +int nx_mlc_get_top_sleep_mode(u32 module_index); +void nx_mlc_set_top_dirty_flag(u32 module_index); +int nx_mlc_get_top_dirty_flag(u32 module_index); +void nx_mlc_set_mlc_enable(u32 module_index, int benb); +int nx_mlc_get_mlc_enable(u32 module_index); +void nx_mlc_set_field_enable(u32 module_index, int benb); +int nx_mlc_get_field_enable(u32 module_index); +void nx_mlc_set_layer_priority(u32 module_index, + enum nx_mlc_priority priority); +void nx_mlc_set_screen_size(u32 module_index, u32 width, u32 height); +void nx_mlc_get_screen_size(u32 module_index, u32 *pwidth, + u32 *pheight); +void nx_mlc_set_background(u32 module_index, u32 color); + +void nx_mlc_set_dirty_flag(u32 module_index, u32 layer); +int nx_mlc_get_dirty_flag(u32 module_index, u32 layer); +void nx_mlc_set_layer_enable(u32 module_index, u32 layer, int benb); +int nx_mlc_get_layer_enable(u32 module_index, u32 layer); +void nx_mlc_set_lock_size(u32 module_index, u32 layer, u32 locksize); +void nx_mlc_set_alpha_blending(u32 module_index, u32 layer, int benb, + u32 alpha); +void nx_mlc_set_transparency(u32 module_index, u32 layer, int benb, + u32 color); +void nx_mlc_set_color_inversion(u32 module_index, u32 layer, int benb, + u32 color); +u32 nx_mlc_get_extended_color(u32 module_index, u32 color, + enum nx_mlc_rgbfmt format); +void nx_mlc_set_format_rgb(u32 module_index, u32 layer, + enum nx_mlc_rgbfmt format); +void nx_mlc_set_format_yuv(u32 module_index, enum nx_mlc_yuvfmt format); +void nx_mlc_set_position(u32 module_index, u32 layer, s32 sx, + s32 sy, s32 ex, s32 ey); +void nx_mlc_set_dither_enable_when_using_gamma(u32 module_index, + int benable); +int nx_mlc_get_dither_enable_when_using_gamma(u32 module_index); +void nx_mlc_set_gamma_priority(u32 module_index, int bvideolayer); +int nx_mlc_get_gamma_priority(u32 module_index); + +void nx_mlc_set_rgblayer_invalid_position(u32 module_index, u32 layer, + u32 region, s32 sx, + s32 sy, s32 ex, + s32 ey, int benb); +void nx_mlc_set_rgblayer_stride(u32 module_index, u32 layer, + s32 hstride, s32 vstride); +void nx_mlc_set_rgblayer_address(u32 module_index, u32 layer, u32 addr); +void nx_mlc_set_rgblayer_gama_table_power_mode(u32 module_index, + int bred, int bgreen, + int bblue); +void nx_mlc_get_rgblayer_gama_table_power_mode(u32 module_index, + int *pbred, int *pbgreen, + int *pbblue); +void nx_mlc_set_rgblayer_gama_table_sleep_mode(u32 module_index, + int bred, int bgreen, + int bblue); +void nx_mlc_get_rgblayer_gama_table_sleep_mode(u32 module_index, + int *pbred, int *pbgreen, + int *pbblue); +void nx_mlc_set_rgblayer_rgamma_table(u32 module_index, u32 dwaddress, + u32 dwdata); +void nx_mlc_set_rgblayer_ggamma_table(u32 module_index, u32 dwaddress, + u32 dwdata); +void nx_mlc_set_rgblayer_bgamma_table(u32 module_index, u32 dwaddress, + u32 dwdata); +void nx_mlc_set_rgblayer_gamma_enable(u32 module_index, int benable); +int nx_mlc_get_rgblayer_gamma_enable(u32 module_index); + +void nx_mlc_set_video_layer_stride(u32 module_index, s32 lu_stride, + s32 cb_stride, s32 cr_stride); +void nx_mlc_set_video_layer_address(u32 module_index, u32 lu_addr, + u32 cb_addr, u32 cr_addr); +void nx_mlc_set_video_layer_address_yuyv(u32 module_index, u32 addr, + s32 stride); +void nx_mlc_set_video_layer_scale_factor(u32 module_index, u32 hscale, + u32 vscale, int bhlumaenb, + int bhchromaenb, int bvlumaenb, + int bvchromaenb); +void nx_mlc_set_video_layer_scale_filter(u32 module_index, int bhlumaenb, + int bhchromaenb, int bvlumaenb, + int bvchromaenb); +void nx_mlc_get_video_layer_scale_filter(u32 module_index, + int *bhlumaenb, + int *bhchromaenb, + int *bvlumaenb, + int *bvchromaenb); +void nx_mlc_set_video_layer_scale(u32 module_index, u32 sw, u32 sh, + u32 dw, u32 dh, int bhlumaenb, + int bhchromaenb, int bvlumaenb, + int bvchromaenb); +void nx_mlc_set_video_layer_luma_enhance(u32 module_index, u32 contrast, + s32 brightness); +void nx_mlc_set_video_layer_chroma_enhance(u32 module_index, + u32 quadrant, s32 cb_a, + s32 cb_b, s32 cr_a, + s32 cr_b); +void nx_mlc_set_video_layer_line_buffer_power_mode(u32 module_index, + int benable); +int nx_mlc_get_video_layer_line_buffer_power_mode(u32 module_index); +void nx_mlc_set_video_layer_line_buffer_sleep_mode(u32 module_index, + int benable); +int nx_mlc_get_video_layer_line_buffer_sleep_mode(u32 module_index); +void nx_mlc_set_video_layer_gamma_enable(u32 module_index, int benable); +int nx_mlc_get_video_layer_gamma_enable(u32 module_index); + +void nx_mlc_set_gamma_table_poweroff(u32 module_index, int enb); + +enum mlc_rgbfmt { + rgbfmt_r5g6b5 = 0, + rgbfmt_x1r5g5b5 = 1, + rgbfmt_x4r4g4b4 = 2, + rgbfmt_x8r3g3b2 = 3, + rgbfmt_x8l8 = 4, + rgbfmt_l16 = 5, + rgbfmt_a1r5g5b5 = 6, + rgbfmt_a4r4g4b4 = 7, + rgbfmt_a8r3g3b2 = 8, + rgbfmt_a8l8 = 9, + rgbfmt_r8g8b8 = 10, + rgbfmt_x8r8g8b8 = 11, + rgbfmt_a8r8g8b8 = 12, + rgbfmt_g8r8_g8b8 = 13, + rgbfmt_r8g8_b8g8 = 14, + rgbfmt_b5g6r5 = 15, + rgbfmt_x1b5g5r5 = 16, + rgbfmt_x4b4g4r4 = 17, + rgbfmt_x8b3g3r2 = 18, + rgbfmt_a1b5g5r5 = 19, + rgbfmt_a4b4g4r4 = 20, + rgbfmt_a8b3g3r2 = 21, + rgbfmt_b8g8r8 = 22, + rgbfmt_x8b8g8r8 = 23, + rgbfmt_a8b8g8r8 = 24, + rgbfmt_g8b8_g8r8 = 25, + rgbfmt_b8g8_r8g8 = 26, + rgbfmt_pataletb = 27 +}; + +enum latyername { + topmlc = 0, + rgb0 = 1, + rgb1 = 2, + rgb2 = 3, + video = 4 +}; + +enum srammode { + poweroff = 0, + sleepmode = 2, + run = 3 +}; + +enum locksizesel { + locksize_4 = 0, + locksize_8 = 1, + locksize_16 = 2 +}; + +enum g3daddrchangeallowed { + prim = 0, + secon = 1, + primorsecon = 2, + primandsecon = 3 +}; + +void nx_mlc_set_mlctop_control_parameter(u32 module_index, + int field_enable, int mlcenable, + u8 priority, + enum g3daddrchangeallowed + g3daddr_change_allowed); +void nx_mlc_set_rgb0layer_control_parameter(u32 module_index, + int layer_enable, + int grp3denable, + int tp_enable, + u32 transparency_color, + int inv_enable, + u32 inverse_color, + int blend_enable, + u8 alpha_value, + enum mlc_rgbfmt rbgformat, + enum locksizesel + lock_size_select); + +u32 nx_mlc_get_rgbformat(enum mlc_rgbfmt rbgformat); +void nx_mlc_set_rgb1layer_control_parameter(u32 module_index, + int layer_enable, + int grp3denable, + int tp_enable, + u32 transparency_color, + int inv_enable, + u32 inverse_color, + int blend_enable, + u8 alpha_value, + enum mlc_rgbfmt rbgformat, + enum locksizesel + lock_size_select); + +void nx_mlc_set_rgb2layer_control_parameter(u32 module_index, + int layer_enable, + int grp3denable, + int tp_enable, + u32 transparency_color, + int inv_enable, + u32 inverse_color, + int blend_enable, + u8 alpha_value, + enum mlc_rgbfmt rbgformat, + enum locksizesel + lock_size_select); + +void nx_mlc_set_video_layer_control_parameter(u32 module_index, + int layer_enable, + int tp_enable, + u32 transparency_color, + int inv_enable, + u32 inverse_color, + int blend_enable, + u8 alpha_value, + enum nx_mlc_yuvfmt + yuvformat); + +void nx_mlc_set_srammode(u32 module_index, enum latyername layer_name, + enum srammode sram_mode); + +void nx_mlc_set_layer_reg_finish(u32 module_index, + enum latyername layer_name); + +void nx_mlc_set_video_layer_coordinate(u32 module_index, + int vfilterenable, + int hfilterenable, + int vfilterenable_c, + int hfilterenable_c, + u16 video_layer_with, + u16 video_layer_height, + s16 left, s16 right, + s16 top, s16 bottom); + +void nx_mlc_set_video_layer_filter_scale(u32 module_index, u32 hscale, + u32 vscale); +void nx_mlcsetgammasrammode(u32 module_index, enum srammode sram_mode); +void nx_mlc_set_gamma_control_parameter(u32 module_index, + int rgbgammaenb, int yuvgammaenb, + int yuvalphaarray, + int dither_enb); + +void nx_mlc_set_layer_alpha256(u32 module_index, u32 layer, u32 alpha); +int nx_mlc_is_under_flow(u32 module_index); + +struct nx_mlc_gamma_table_parameter { + u32 r_table[256]; + u32 g_table[256]; + u32 b_table[256]; + u32 ditherenb; + u32 alphaselect; + u32 yuvgammaenb; + u32 rgbgammaenb; + u32 allgammaenb; +}; + +void nx_mlc_set_gamma_table(u32 module_index, int enb, + struct nx_mlc_gamma_table_parameter *p_gammatable); +void nx_mlc_get_rgblayer_stride(u32 module_index, u32 layer, + s32 *hstride, s32 *vstride); +void nx_mlc_get_rgblayer_address(u32 module_index, u32 layer, + u32 *phys_address); +void nx_mlc_get_position(u32 module_index, u32 layer, int *left, + int *top, int *right, int *bottom); +void nx_mlc_get_video_layer_address_yuyv(u32 module_index, u32 *address, + u32 *stride); +void nx_mlc_get_video_layer_address(u32 module_index, u32 *lu_address, + u32 *cb_address, u32 *cr_address); +void nx_mlc_get_video_layer_stride(u32 module_index, u32 *lu_stride, + u32 *cb_stride, u32 *cr_stride); +void nx_mlc_get_video_layer_stride(u32 module_index, u32 *lu_stride, + u32 *cb_stride, u32 *cr_stride); +void nx_mlc_get_video_position(u32 module_index, int *left, int *top, + int *right, int *bottom); + +#endif