From patchwork Thu Mar 12 13:23:50 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Ang, Chee Hong" X-Patchwork-Id: 243585 List-Id: U-Boot discussion From: chee.hong.ang at intel.com (chee.hong.ang at intel.com) Date: Thu, 12 Mar 2020 06:23:50 -0700 Subject: [PATCH v5 13/17] arm: socfpga: stratix10: Initialize timer in SPL In-Reply-To: <1584019434-45856-1-git-send-email-chee.hong.ang@intel.com> References: <1584019434-45856-1-git-send-email-chee.hong.ang@intel.com> Message-ID: <1584019434-45856-14-git-send-email-chee.hong.ang@intel.com> From: Chee Hong Ang Initialize timer in SPL running in secure mode (EL3) and skip timer initialization in U-Boot proper running in non-secure mode (EL2). Signed-off-by: Chee Hong Ang --- arch/arm/mach-socfpga/timer_s10.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-socfpga/timer_s10.c b/arch/arm/mach-socfpga/timer_s10.c index 5723789..0fa56c3 100644 --- a/arch/arm/mach-socfpga/timer_s10.c +++ b/arch/arm/mach-socfpga/timer_s10.c @@ -13,6 +13,7 @@ */ int timer_init(void) { +#ifdef CONFIG_SPL_BUILD int enable = 0x3; /* timer enable + output signal masked */ int loadval = ~0; @@ -21,6 +22,6 @@ int timer_init(void) /* enable processor pysical counter */ asm volatile("msr cntp_ctl_el0, %0" : : "r" (enable)); asm volatile("msr cntp_tval_el0, %0" : : "r" (loadval)); - +#endif return 0; }