From patchwork Thu Mar 12 13:23:47 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Ang, Chee Hong" X-Patchwork-Id: 243581 List-Id: U-Boot discussion From: chee.hong.ang at intel.com (chee.hong.ang at intel.com) Date: Thu, 12 Mar 2020 06:23:47 -0700 Subject: [PATCH v5 10/17] mmc: dwmmc: socfpga: Add ATF support for MMC driver In-Reply-To: <1584019434-45856-1-git-send-email-chee.hong.ang@intel.com> References: <1584019434-45856-1-git-send-email-chee.hong.ang@intel.com> Message-ID: <1584019434-45856-11-git-send-email-chee.hong.ang@intel.com> From: Chee Hong Ang In non-secure mode (EL2), MMC driver calls the SMC/PSCI services provided by ATF to set SDMMC's DRVSEL and SMPLSEL. Signed-off-by: Chee Hong Ang --- drivers/mmc/socfpga_dw_mmc.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/drivers/mmc/socfpga_dw_mmc.c b/drivers/mmc/socfpga_dw_mmc.c index 786cdc7..d4d1132 100644 --- a/drivers/mmc/socfpga_dw_mmc.c +++ b/drivers/mmc/socfpga_dw_mmc.c @@ -5,13 +5,16 @@ #include #include +#include #include #include #include #include #include #include +#include #include +#include #include #include #include @@ -45,6 +48,20 @@ static void socfpga_dwmci_reset(struct udevice *dev) reset_deassert_bulk(&reset_bulk); } +#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF) +static void socfpga_dwmci_fw_clksel(u32 sdmmc_mask) +{ + u64 args[2]; + + /* drvsel */ + args[0] = (sdmmc_mask >> SYSMGR_SDMMC_DRVSEL_SHIFT) & 0x7; + /* smplsel */ + args[1] = (sdmmc_mask >> SYSMGR_SDMMC_SMPLSEL_SHIFT) & 0x7; + if (invoke_smc(INTEL_SIP_SMC_HPS_SET_SDMMC_CCLK, args, 2, NULL, 0)) + hang(); +} +#endif + static void socfpga_dwmci_clksel(struct dwmci_host *host) { struct dwmci_socfpga_priv_data *priv = host->priv; @@ -57,10 +74,14 @@ static void socfpga_dwmci_clksel(struct dwmci_host *host) debug("%s: drvsel %d smplsel %d\n", __func__, priv->drvsel, priv->smplsel); +#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF) + socfpga_dwmci_fw_clksel(sdmmc_mask); +#else writel(sdmmc_mask, socfpga_get_sysmgr_addr() + SYSMGR_SDMMC); debug("%s: SYSMGR_SDMMCGRP_CTRL_REG = 0x%x\n", __func__, readl(socfpga_get_sysmgr_addr() + SYSMGR_SDMMC)); +#endif /* Enable SDMMC clock */ setbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_PERPLL_EN,