From patchwork Mon Mar 9 09:07:16 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Ang, Chee Hong" X-Patchwork-Id: 243434 List-Id: U-Boot discussion From: chee.hong.ang at intel.com (chee.hong.ang at intel.com) Date: Mon, 9 Mar 2020 02:07:16 -0700 Subject: [PATCH v4 15/21] net: designware: socfpga: MAC driver access System Manager via 'altera_sysmgr' In-Reply-To: <1583744842-24632-1-git-send-email-chee.hong.ang@intel.com> References: <1583744842-24632-1-git-send-email-chee.hong.ang@intel.com> Message-ID: <1583744842-24632-16-git-send-email-chee.hong.ang@intel.com> From: Chee Hong Ang MAC driver now access System Manger's EMAC0/EMAC1/EMAC2 registers to set PHY mode via 'altera_sysmgr' driver. Signed-off-by: Chee Hong Ang --- drivers/net/dwmac_socfpga.c | 37 +++++++++++++++++-------------------- 1 file changed, 17 insertions(+), 20 deletions(-) diff --git a/drivers/net/dwmac_socfpga.c b/drivers/net/dwmac_socfpga.c index e93561d..c825cbf 100644 --- a/drivers/net/dwmac_socfpga.c +++ b/drivers/net/dwmac_socfpga.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include @@ -21,16 +22,14 @@ struct dwmac_socfpga_platdata { struct dw_eth_pdata dw_eth_pdata; - void *phy_intf; + fdt_addr_t phy_reg_offset; u32 reg_shift; }; static int dwmac_socfpga_ofdata_to_platdata(struct udevice *dev) { struct dwmac_socfpga_platdata *pdata = dev_get_platdata(dev); - struct regmap *regmap; struct ofnode_phandle_args args; - void *range; int ret; ret = dev_read_phandle_with_args(dev, "altr,sysmgr-syscon", NULL, @@ -45,20 +44,7 @@ static int dwmac_socfpga_ofdata_to_platdata(struct udevice *dev) return -EINVAL; } - regmap = syscon_node_to_regmap(args.node); - if (IS_ERR(regmap)) { - ret = PTR_ERR(regmap); - dev_err(dev, "Failed to get regmap: %d\n", ret); - return ret; - } - - range = regmap_get_range(regmap, 0); - if (!range) { - dev_err(dev, "Failed to get regmap range\n"); - return -ENOMEM; - } - - pdata->phy_intf = range + args.args[0]; + pdata->phy_reg_offset = args.args[0]; pdata->reg_shift = args.args[1]; return designware_eth_ofdata_to_platdata(dev); @@ -69,10 +55,20 @@ static int dwmac_socfpga_probe(struct udevice *dev) struct dwmac_socfpga_platdata *pdata = dev_get_platdata(dev); struct eth_pdata *edata = &pdata->dw_eth_pdata.eth_pdata; struct reset_ctl_bulk reset_bulk; + struct udevice *sysmgr; int ret; u32 modereg; u32 modemask; + ret = uclass_get_device_by_phandle(UCLASS_MISC, dev, + "altr,sysmgr-syscon", &sysmgr); + + if (ret == -ENOENT) { + debug("%s: Could not find 'altr,sysmgr-syscon' phandle\n", + dev->name); + return -EINVAL; + } + switch (edata->phy_interface) { case PHY_INTERFACE_MODE_MII: case PHY_INTERFACE_MODE_GMII: @@ -97,9 +93,10 @@ static int dwmac_socfpga_probe(struct udevice *dev) reset_assert_bulk(&reset_bulk); - modemask = SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << pdata->reg_shift; - clrsetbits_le32(pdata->phy_intf, modemask, - modereg << pdata->reg_shift); + misc_read(sysmgr, pdata->phy_reg_offset, &modemask, sizeof(modemask)); + modemask &= ~(SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << pdata->reg_shift); + modemask |= (modereg << pdata->reg_shift); + misc_write(sysmgr, pdata->phy_reg_offset, &modemask, sizeof(modemask)); reset_release_bulk(&reset_bulk);