From patchwork Mon Mar 2 11:09:19 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kuldeep Singh X-Patchwork-Id: 243165 List-Id: U-Boot discussion From: kuldeep.singh at nxp.com (Kuldeep Singh) Date: Mon, 2 Mar 2020 16:39:19 +0530 Subject: [Patch v2] arm: dts: lx2160aqds: Add FSPI node properties Message-ID: <1583147359-6446-1-git-send-email-kuldeep.singh@nxp.com> lx2160a-qds has 2 micron "mt35xu512aba" flashes of size 64M each connected on A0 and B1 i.e on CS0 and CS3. Since flashes are connected on different buses, only one flash can be probed at a time. Add fspi node properties aligned with LX2160A-RDB fspi properties. Signed-off-by: Kuldeep Singh --- v2: Update flash nodes as per compatibles arch/arm/dts/fsl-lx2160a-qds.dts | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm/dts/fsl-lx2160a-qds.dts b/arch/arm/dts/fsl-lx2160a-qds.dts index 34df0f5..33bedae 100644 --- a/arch/arm/dts/fsl-lx2160a-qds.dts +++ b/arch/arm/dts/fsl-lx2160a-qds.dts @@ -13,6 +13,9 @@ / { model = "NXP Layerscape LX2160AQDS Board"; compatible = "fsl,lx2160aqds", "fsl,lx2160a"; + aliases { + spi0 = &fspi; + }; }; &esdhc0 { @@ -46,6 +49,18 @@ }; }; +&fspi { + status = "okay"; + + mt35xu512aba0: flash at 0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <50000000>; + reg = <0>; + }; +}; + &sata0 { status = "okay"; };