From patchwork Fri Feb 21 05:47:32 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Ang, Chee Hong" X-Patchwork-Id: 236687 List-Id: U-Boot discussion From: chee.hong.ang at intel.com (chee.hong.ang at intel.com) Date: Thu, 20 Feb 2020 21:47:32 -0800 Subject: [PATCH v3 14/21] mmc: dwmmc: socfpga: Secure register access in MMC driver In-Reply-To: <1582264059-37988-1-git-send-email-chee.hong.ang@intel.com> References: <1582264059-37988-1-git-send-email-chee.hong.ang@intel.com> Message-ID: <1582264059-37988-15-git-send-email-chee.hong.ang@intel.com> From: Chee Hong Ang Allow MMC driver to access System Manager's SDMMC control register in non-secure mode (EL2). Signed-off-by: Chee Hong Ang --- drivers/mmc/socfpga_dw_mmc.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/mmc/socfpga_dw_mmc.c b/drivers/mmc/socfpga_dw_mmc.c index 786cdc7..558f246 100644 --- a/drivers/mmc/socfpga_dw_mmc.c +++ b/drivers/mmc/socfpga_dw_mmc.c @@ -5,6 +5,7 @@ #include #include +#include #include #include #include @@ -57,10 +58,12 @@ static void socfpga_dwmci_clksel(struct dwmci_host *host) debug("%s: drvsel %d smplsel %d\n", __func__, priv->drvsel, priv->smplsel); - writel(sdmmc_mask, socfpga_get_sysmgr_addr() + SYSMGR_SDMMC); + socfpga_secure_reg_write32(sdmmc_mask, socfpga_get_sysmgr_addr() + + SYSMGR_SDMMC); debug("%s: SYSMGR_SDMMCGRP_CTRL_REG = 0x%x\n", __func__, - readl(socfpga_get_sysmgr_addr() + SYSMGR_SDMMC)); + socfpga_secure_reg_read32(socfpga_get_sysmgr_addr() + + SYSMGR_SDMMC)); /* Enable SDMMC clock */ setbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_PERPLL_EN,