@@ -53,6 +53,10 @@ obj-y += wrap_pinmux_config_s10.o
obj-y += wrap_pll_config_s10.o
endif
+ifndef CONFIG_SPL_BUILD
+obj-$(CONFIG_SPL_ATF) +=secure_reg_helper.o
+endif
+
ifdef CONFIG_SPL_BUILD
ifdef CONFIG_TARGET_SOCFPGA_GEN5
obj-y += spl_gen5.o
new file mode 100644
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (C) 2019 Intel Corporation <www.intel.com>
+ *
+ */
+
+#ifndef _SECURE_REG_HELPER_H_
+#define _SECURE_REG_HELPER_H_
+
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF)
+u32 socfpga_secure_reg_read32(phys_addr_t reg_addr);
+void socfpga_secure_reg_write32(u32 val, phys_addr_t reg_addr);
+void socfpga_secure_reg_update32(phys_addr_t reg_addr, u32 mask, u32 val);
+#else
+#define socfpga_secure_reg_read32 readl
+#define socfpga_secure_reg_write32 writel
+#define socfpga_secure_reg_update32 clrsetbits_le32
+#endif
+
+#endif /* _SECURE_REG_HELPER_H_ */
new file mode 100644
@@ -0,0 +1,57 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 Intel Corporation <www.intel.com>
+ *
+ */
+
+#include <common.h>
+#include <hang.h>
+#include <asm/io.h>
+#include <asm/system.h>
+#include <asm/arch/misc.h>
+#include <linux/intel-smc.h>
+
+u32 socfpga_secure_reg_read32(phys_addr_t reg_addr)
+{
+ int ret;
+ u64 ret_arg;
+ u64 args[1];
+
+ args[0] = (u64)reg_addr;
+ ret = invoke_smc(INTEL_SIP_SMC_REG_READ, args, 1, &ret_arg, 1);
+ if (ret) {
+ /* SMC call return error */
+ hang();
+ }
+
+ return ret_arg;
+}
+
+void socfpga_secure_reg_write32(u32 val, phys_addr_t reg_addr)
+{
+ int ret;
+ u64 args[2];
+
+ args[0] = (u64)reg_addr;
+ args[1] = val;
+ ret = invoke_smc(INTEL_SIP_SMC_REG_WRITE, args, 2, NULL, 0);
+ if (ret) {
+ /* SMC call return error */
+ hang();
+ }
+}
+
+void socfpga_secure_reg_update32(phys_addr_t reg_addr, u32 mask, u32 val)
+{
+ int ret;
+ u64 args[3];
+
+ args[0] = (u64)reg_addr;
+ args[1] = mask;
+ args[2] = val;
+ ret = invoke_smc(INTEL_SIP_SMC_REG_UPDATE, args, 3, NULL, 0);
+ if (ret) {
+ /* SMC call return error */
+ hang();
+ }
+}