From patchwork Wed Feb 19 12:25:37 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Ang, Chee Hong" X-Patchwork-Id: 236570 List-Id: U-Boot discussion From: chee.hong.ang at intel.com (chee.hong.ang at intel.com) Date: Wed, 19 Feb 2020 04:25:37 -0800 Subject: [PATCH v2 12/21] arm: socfpga: Secure register access in PHY mode setup In-Reply-To: <1582115146-28658-1-git-send-email-chee.hong.ang@intel.com> References: <1582115146-28658-1-git-send-email-chee.hong.ang@intel.com> Message-ID: <1582115146-28658-13-git-send-email-chee.hong.ang@intel.com> From: Chee Hong Ang Allow access to System Manager's EMAC control register from non-secure mode during PHY mode setup. Signed-off-by: Chee Hong Ang --- arch/arm/mach-socfpga/misc_s10.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-socfpga/misc_s10.c b/arch/arm/mach-socfpga/misc_s10.c index 25c3ff6..6593308 100644 --- a/arch/arm/mach-socfpga/misc_s10.c +++ b/arch/arm/mach-socfpga/misc_s10.c @@ -18,6 +18,7 @@ #include #include #include +#include #include @@ -65,9 +66,9 @@ static u32 socfpga_phymode_setup(u32 gmac_index, const char *phymode) else return -EINVAL; - clrsetbits_le32(socfpga_get_sysmgr_addr() + SYSMGR_SOC64_EMAC0 + - gmac_index, - SYSMGR_EMACGRP_CTRL_PHYSEL_MASK, modereg); + socfpga_secure_reg_update32(socfpga_get_sysmgr_addr() + + SYSMGR_SOC64_EMAC0 + gmac_index, + SYSMGR_EMACGRP_CTRL_PHYSEL_MASK, modereg); return 0; }