From patchwork Mon Jan 6 08:09:04 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Tan, Ley Foon" X-Patchwork-Id: 239135 List-Id: U-Boot discussion From: ley.foon.tan at intel.com (Ley Foon Tan) Date: Mon, 6 Jan 2020 16:09:04 +0800 Subject: [PATCH v3] reset: socfpga: Poll for reset status after deassert reset Message-ID: <1578298144-30200-1-git-send-email-ley.foon.tan@intel.com> In Cyclone 5 SoC platform, the first USB probing is failed but second probing is success. DWC2 USB driver read gsnpsid register right after de-assert reset, but controller is not ready yet and it returns gsnpsid 0. Polling reset status after de-assert reset to solve the issue. Retry with this fix more than 10 times without issue. Signed-off-by: Ley Foon Tan --- v3: - Remove _status callback and poll reset status after deassert reset v2: - https://patchwork.ozlabs.org/cover/1215174/ v1: - https://patchwork.ozlabs.org/patch/1214841/ --- drivers/reset/reset-socfpga.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/drivers/reset/reset-socfpga.c b/drivers/reset/reset-socfpga.c index 93ec9cfdb6..172028dcf6 100644 --- a/drivers/reset/reset-socfpga.c +++ b/drivers/reset/reset-socfpga.c @@ -78,9 +78,20 @@ static int socfpga_reset_deassert(struct reset_ctl *reset_ctl) int reg_width = sizeof(u32); int bank = id / (reg_width * BITS_PER_BYTE); int offset = id % (reg_width * BITS_PER_BYTE); + int i = 1000; + u32 status; clrbits_le32(data->modrst_base + (bank * BANK_INCREMENT), BIT(offset)); - return 0; + + /* Poll until reset is completed. */ + do { + status = readl(data->modrst_base + (bank * BANK_INCREMENT)) & + BIT(offset); + if (!status) + return 0; + } while (i--); + + return -ETIMEDOUT; } static int socfpga_reset_request(struct reset_ctl *reset_ctl)