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[81.169.180.215]) by mx.google.com with ESMTP id r17-v6si2064239edd.405.2018.09.09.20.59.51; Sun, 09 Sep 2018 20:59:51 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@nifty.com header.s=dec2015msa header.b=nte4788W; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by lists.denx.de (Postfix, from userid 105) id 1A49CC21E1D; Mon, 10 Sep 2018 03:59:31 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 6027AC21DFA; Mon, 10 Sep 2018 03:59:18 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id B3269C21E1E; Mon, 10 Sep 2018 03:59:15 +0000 (UTC) Received: from conuserg-12.nifty.com (conuserg-12.nifty.com [210.131.2.79]) by lists.denx.de (Postfix) with ESMTPS id 69EAFC21DCA for ; Mon, 10 Sep 2018 03:59:09 +0000 (UTC) Received: from pug.e01.socionext.com (p14092-ipngnfx01kyoto.kyoto.ocn.ne.jp [153.142.97.92]) (authenticated) by conuserg-12.nifty.com with ESMTP id w8A3wifZ006634; Mon, 10 Sep 2018 12:58:47 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-12.nifty.com w8A3wifZ006634 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1536551927; bh=Les2PnRctCo66cRjtPxO3XDAL7rSPFV68CFoO92bExY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=nte4788WMaZpjp2E0cGOAHSLT1agB7481GOjPu9KgaJYGE3jij1Wvw6X8y2HocIc3 79pWNKhKsUDktD6ddQRCerqvgT5T3JQHJX5tvWrC0RI5JV56HVJ3ML+X72etvhlgCZ mmOGRhU7WngZKjChr7SR78lxCxZvUC+ZPBWhTuK8tCclW0TSpbuDOSYORGupRF1dt7 lWRpXkfAzDU9ZyHRDh9wb6wq44ZNAviOCEWzGkGyj4tsvbXphdFVpcg/eEOpN8sj40 a7ZrK8A/VKf0BxX/89WybcALlzuZWeH0VbDF1/lmELhmmmJ5KD2r8r6iSZlvy7MQIy 0sQ7dh8Lt08lw== X-Nifty-SrcIP: [153.142.97.92] From: Masahiro Yamada To: u-boot@lists.denx.de Date: Mon, 10 Sep 2018 12:58:36 +0900 Message-Id: <1536551916-21187-6-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1536551916-21187-1-git-send-email-yamada.masahiro@socionext.com> References: <1536551916-21187-1-git-send-email-yamada.masahiro@socionext.com> Cc: Tom Rini Subject: [U-Boot] [PATCH 5/5] ARM: uniphier: remove ad-hoc clock enabling for EHCI X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" The MIO clock is enabled by default, and the STDMAC clock is enabled by the clk driver. The ad-hoc way to enable the clock is no longer needed. Signed-off-by: Masahiro Yamada --- arch/arm/mach-uniphier/clk/clk-ld11.c | 6 ------ arch/arm/mach-uniphier/clk/clk-ld4.c | 3 --- arch/arm/mach-uniphier/clk/clk-pro4.c | 3 --- arch/arm/mach-uniphier/sc-regs.h | 3 --- 4 files changed, 15 deletions(-) diff --git a/arch/arm/mach-uniphier/clk/clk-ld11.c b/arch/arm/mach-uniphier/clk/clk-ld11.c index ec5fa7b..e997acf 100644 --- a/arch/arm/mach-uniphier/clk/clk-ld11.c +++ b/arch/arm/mach-uniphier/clk/clk-ld11.c @@ -34,14 +34,8 @@ void uniphier_ld11_clk_init(void) #ifdef CONFIG_USB_EHCI_HCD { - /* FIXME: the current clk driver can not handle parents */ - u32 tmp; int ch; - tmp = readl(SC_CLKCTRL4); - tmp |= BIT(10) | BIT(8); /* MIO, STDMAC */ - writel(tmp, SC_CLKCTRL4); - for (ch = 0; ch < 3; ch++) { void __iomem *phyctrl = (void __iomem *)SG_USBPHYCTRL; diff --git a/arch/arm/mach-uniphier/clk/clk-ld4.c b/arch/arm/mach-uniphier/clk/clk-ld4.c index d90fef0..9c88cde 100644 --- a/arch/arm/mach-uniphier/clk/clk-ld4.c +++ b/arch/arm/mach-uniphier/clk/clk-ld4.c @@ -24,9 +24,6 @@ void uniphier_ld4_clk_init(void) /* provide clocks */ tmp = readl(SC_CLKCTRL); -#ifdef CONFIG_USB_EHCI_HCD - tmp |= SC_CLKCTRL_CEN_MIO | SC_CLKCTRL_CEN_STDMAC; -#endif #ifdef CONFIG_NAND_DENALI tmp |= SC_CLKCTRL_CEN_NAND; #endif diff --git a/arch/arm/mach-uniphier/clk/clk-pro4.c b/arch/arm/mach-uniphier/clk/clk-pro4.c index e73bf38..32d44c0 100644 --- a/arch/arm/mach-uniphier/clk/clk-pro4.c +++ b/arch/arm/mach-uniphier/clk/clk-pro4.c @@ -39,9 +39,6 @@ void uniphier_pro4_clk_init(void) tmp |= SC_CLKCTRL_CEN_USB31 | SC_CLKCTRL_CEN_USB30 | SC_CLKCTRL_CEN_GIO; #endif -#ifdef CONFIG_USB_EHCI_HCD - tmp |= SC_CLKCTRL_CEN_MIO | SC_CLKCTRL_CEN_STDMAC; -#endif #ifdef CONFIG_NAND_DENALI tmp |= SC_CLKCTRL_CEN_NAND; #endif diff --git a/arch/arm/mach-uniphier/sc-regs.h b/arch/arm/mach-uniphier/sc-regs.h index c5c054e..b105335 100644 --- a/arch/arm/mach-uniphier/sc-regs.h +++ b/arch/arm/mach-uniphier/sc-regs.h @@ -42,7 +42,6 @@ #define SC_RSTCTRL_NRST_USB3B0 (0x1 << 17) /* USB3 #0 bus */ #define SC_RSTCTRL_NRST_USB3C0 (0x1 << 16) /* USB3 #0 core */ #define SC_RSTCTRL_NRST_ETHER (0x1 << 12) -#define SC_RSTCTRL_NRST_STDMAC (0x1 << 10) #define SC_RSTCTRL_NRST_GIO (0x1 << 6) /* Pro4 or older */ #define SC_RSTCTRL_NRST_UMC1 (0x1 << 5) @@ -73,8 +72,6 @@ #define SC_CLKCTRL_CEN_USB31 (0x1 << 17) /* USB3 #1 */ #define SC_CLKCTRL_CEN_USB30 (0x1 << 16) /* USB3 #0 */ #define SC_CLKCTRL_CEN_ETHER (0x1 << 12) -#define SC_CLKCTRL_CEN_MIO (0x1 << 11) -#define SC_CLKCTRL_CEN_STDMAC (0x1 << 10) #define SC_CLKCTRL_CEN_GIO (0x1 << 6) /* Pro4 or older */ #define SC_CLKCTRL_CEN_UMC (0x1 << 4)