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[81.169.180.215]) by mx.google.com with ESMTP id f5-v6si669374edj.330.2018.07.19.00.31.00; Thu, 19 Jul 2018 00:31:00 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@nifty.com header.s=dec2015msa header.b=OfEvmFIr; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by lists.denx.de (Postfix, from userid 105) id 44DE3C21FBC; Thu, 19 Jul 2018 07:29:38 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 28FF8C21FCE; Thu, 19 Jul 2018 07:29:08 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id D9413C21FCD; Thu, 19 Jul 2018 07:28:54 +0000 (UTC) Received: from conuserg-11.nifty.com (conuserg-11.nifty.com [210.131.2.78]) by lists.denx.de (Postfix) with ESMTPS id A4ACAC21FC0 for ; Thu, 19 Jul 2018 07:28:50 +0000 (UTC) Received: from pug.e01.socionext.com (p14092-ipngnfx01kyoto.kyoto.ocn.ne.jp [153.142.97.92]) (authenticated) by conuserg-11.nifty.com with ESMTP id w6J7STUD021119; Thu, 19 Jul 2018 16:28:32 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-11.nifty.com w6J7STUD021119 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1531985312; bh=8EB8NGqNlf60UZIcPm9BXGLzAh6/Zx9YtPnJBt6po7U=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=OfEvmFIrRgmdjL8aWdA7/3xW5nA0KDz/TCh9r3dpAd2K+13AwcWqp7RNBWxECUBEz SF7BdEyBCm3OwJIF1EmrpbP1yRiSSNQVUwV2iElCdnzvo6TLTPJ8dvseh5BP60EAXB 4HxbLSBSNz3Rcb53fMD5ABBEbkJPG4N4/Z+g655sbiM/gw05Qa9+KuA356qhL723RV p5BSFMETNL06+Dhcf/CKDdB//WP95cHE1uakNRL31nMd5anuBD3DpzKFKh9/y2DB3V 8vRLfLbGOgbytJFMUmf2P3V1/+fHQTAbFdTlaftnU4PWcJj+tvTSBCix8iB+tkzhk1 y29pL8Bb4jVTg== X-Nifty-SrcIP: [153.142.97.92] From: Masahiro Yamada To: u-boot@lists.denx.de Date: Thu, 19 Jul 2018 16:28:25 +0900 Message-Id: <1531985307-4208-4-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1531985307-4208-1-git-send-email-yamada.masahiro@socionext.com> References: <1531985307-4208-1-git-send-email-yamada.masahiro@socionext.com> Cc: Tom Rini Subject: [U-Boot] [PATCH 4/6] ARM: uniphier: split ft_board_setup() out to a separate file X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Prepare to add more fdt fixup code. Signed-off-by: Masahiro Yamada --- arch/arm/Kconfig | 1 + arch/arm/mach-uniphier/Kconfig | 1 - arch/arm/mach-uniphier/Makefile | 1 + arch/arm/mach-uniphier/dram_init.c | 35 ------------------------ arch/arm/mach-uniphier/fdt-fixup.c | 56 ++++++++++++++++++++++++++++++++++++++ 5 files changed, 58 insertions(+), 36 deletions(-) create mode 100644 arch/arm/mach-uniphier/fdt-fixup.c diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 5b3746c..ebd7c9a 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1221,6 +1221,7 @@ config ARCH_UNIPHIER select DM_RESET select DM_SERIAL select DM_USB + select OF_BOARD_SETUP select OF_CONTROL select OF_LIBFDT select PINCTRL diff --git a/arch/arm/mach-uniphier/Kconfig b/arch/arm/mach-uniphier/Kconfig index 91bea77..c199374 100644 --- a/arch/arm/mach-uniphier/Kconfig +++ b/arch/arm/mach-uniphier/Kconfig @@ -68,7 +68,6 @@ config ARCH_UNIPHIER_LD11 config ARCH_UNIPHIER_LD20 bool "Enable UniPhier LD20 SoC support" depends on ARCH_UNIPHIER_V8_MULTI - select OF_BOARD_SETUP default y config ARCH_UNIPHIER_PXS3 diff --git a/arch/arm/mach-uniphier/Makefile b/arch/arm/mach-uniphier/Makefile index 269c51b..d0c39d42 100644 --- a/arch/arm/mach-uniphier/Makefile +++ b/arch/arm/mach-uniphier/Makefile @@ -21,6 +21,7 @@ endif obj-$(CONFIG_MICRO_SUPPORT_CARD) += sbc/ micro-support-card.o obj-y += pinctrl-glue.o obj-$(CONFIG_MMC) += mmc-first-dev.o +obj-y += fdt-fixup.o endif diff --git a/arch/arm/mach-uniphier/dram_init.c b/arch/arm/mach-uniphier/dram_init.c index 8aa3f81..7e7c1d9 100644 --- a/arch/arm/mach-uniphier/dram_init.c +++ b/arch/arm/mach-uniphier/dram_init.c @@ -6,8 +6,6 @@ */ #include -#include -#include #include #include #include @@ -264,36 +262,3 @@ int dram_init_banksize(void) return 0; } - -#ifdef CONFIG_OF_BOARD_SETUP -/* - * The DRAM PHY requires 64 byte scratch area in each DRAM channel - * for its dynamic PHY training feature. - */ -int ft_board_setup(void *fdt, bd_t *bd) -{ - unsigned long rsv_addr; - const unsigned long rsv_size = 64; - int i, ret; - - if (uniphier_get_soc_id() != UNIPHIER_LD20_ID) - return 0; - - for (i = 0; i < ARRAY_SIZE(bd->bi_dram); i++) { - if (!bd->bi_dram[i].size) - continue; - - rsv_addr = bd->bi_dram[i].start + bd->bi_dram[i].size; - rsv_addr -= rsv_size; - - ret = fdt_add_mem_rsv(fdt, rsv_addr, rsv_size); - if (ret) - return -ENOSPC; - - pr_notice(" Reserved memory region for DRAM PHY training: addr=%lx size=%lx\n", - rsv_addr, rsv_size); - } - - return 0; -} -#endif diff --git a/arch/arm/mach-uniphier/fdt-fixup.c b/arch/arm/mach-uniphier/fdt-fixup.c new file mode 100644 index 0000000..022e442 --- /dev/null +++ b/arch/arm/mach-uniphier/fdt-fixup.c @@ -0,0 +1,56 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2016-2018 Socionext Inc. + * Author: Masahiro Yamada + */ + +#include +#include +#include +#include +#include + +#include "soc-info.h" + +/* + * The DRAM PHY requires 64 byte scratch area in each DRAM channel + * for its dynamic PHY training feature. + */ +static int uniphier_ld20_fdt_mem_rsv(void *fdt, bd_t *bd) +{ + unsigned long rsv_addr; + const unsigned long rsv_size = 64; + int i, ret; + + if (!IS_ENABLED(CONFIG_ARCH_UNIPHIER_LD20) || + uniphier_get_soc_id() != UNIPHIER_LD20_ID) + return 0; + + for (i = 0; i < ARRAY_SIZE(bd->bi_dram); i++) { + if (!bd->bi_dram[i].size) + continue; + + rsv_addr = bd->bi_dram[i].start + bd->bi_dram[i].size; + rsv_addr -= rsv_size; + + ret = fdt_add_mem_rsv(fdt, rsv_addr, rsv_size); + if (ret) + return -ENOSPC; + + pr_notice(" Reserved memory region for DRAM PHY training: addr=%lx size=%lx\n", + rsv_addr, rsv_size); + } + + return 0; +} + +int ft_board_setup(void *fdt, bd_t *bd) +{ + int ret; + + ret = uniphier_ld20_fdt_mem_rsv(fdt, bd); + if (ret) + return ret; + + return 0; +}