From patchwork Tue Jun 19 07:11:45 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 139095 Delivered-To: patch@linaro.org Received: by 2002:a2e:970d:0:0:0:0:0 with SMTP id r13-v6csp4860818lji; Tue, 19 Jun 2018 00:14:26 -0700 (PDT) X-Google-Smtp-Source: ADUXVKIAjnfBTdtDIFDcFTQHwlcDlocRQefM3HCmDsn/ebLpuGc5iw30aSWjN6qYP6M5PtX8q+5T X-Received: by 2002:a50:98e4:: with SMTP id j91-v6mr13763096edb.212.1529392466679; Tue, 19 Jun 2018 00:14:26 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1529392466; cv=none; d=google.com; s=arc-20160816; b=nFbyeVKLEmlhdG8srBitA/jHcO+u2ISx1KfTjRWxDAKzNvTIkAotWdUnJNzBCKsYk4 cJom+WlArfoBNpMZVygZbxZb2k8pfcmlj4FNHiD8GBdrad7M6t4frfcfBCG4riquw009 V69C7qePzHTZEyuExm9yVgNOFSZb1J5g4m0DgIuFG7VJ6BOvMST9nMKVb82nQziyfZL8 k0COGgVHuzfh1nDmlsNDORDk1PuPX/m7YkRsZyyoHuD4YKAna4zcGmy8Da2T4KszxUdv ukMapP3MlrM0bQ7s8oRxEbV+Bx8t9jccPpJIx3CJSr2Fp7V9cTVWW2Pl/qZi27y96MnW r4Ww== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:references:in-reply-to:message-id:date :to:from:dkim-signature:dkim-filter:arc-authentication-results; bh=ja2XAdyPPEGgxLNO4gl9MBhbyuyngx6EqTZZZmsEwos=; b=B2MxQ6lpI4XlLA8ue1rkkS0wSgMlkvOlUCqBSsuBQFlYNA4yERt1qTwWG0OLRyMWQ7 dWG96+reMMxLNlVcFZAFmNaDIhR8XnmIH7NRlOzMv1hf2+A5e0usxymdAX9y4mh4dcSU A62MHOq9FT0/66EDBQJGMIuE4r4WWW3AM9fY0iMt7m05a5zykcRRaBySO92LQsOY/eqt 9aSMPUEf6FbSt0GynyyAOiW9trXN1qprEhKjPYL6xr9PHyDUKTyYNHvkq2wtUlgPE0JF 1CuqyrBSAOMAwEVZjw6hsiVwEY6VUcgz8P8m8w4gWJuTM2KCldOmZjMri26/mrH4iPlr Boow== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@nifty.com header.s=dec2015msa header.b=t7xYg6hg; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Return-Path: Received: from lists.denx.de (dione.denx.de. [81.169.180.215]) by mx.google.com with ESMTP id c5-v6si6501492edf.296.2018.06.19.00.14.26; Tue, 19 Jun 2018 00:14:26 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@nifty.com header.s=dec2015msa header.b=t7xYg6hg; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by lists.denx.de (Postfix, from userid 105) id 3F143C21FB6; Tue, 19 Jun 2018 07:12:43 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id CB1C8C21FC0; Tue, 19 Jun 2018 07:12:09 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 37041C21F3D; Tue, 19 Jun 2018 07:12:06 +0000 (UTC) Received: from conuserg-09.nifty.com (conuserg-09.nifty.com [210.131.2.76]) by lists.denx.de (Postfix) with ESMTPS id 2D31CC21FA4 for ; Tue, 19 Jun 2018 07:12:02 +0000 (UTC) Received: from pug.e01.socionext.com (p14092-ipngnfx01kyoto.kyoto.ocn.ne.jp [153.142.97.92]) (authenticated) by conuserg-09.nifty.com with ESMTP id w5J7BnbF015508; Tue, 19 Jun 2018 16:11:51 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-09.nifty.com w5J7BnbF015508 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1529392311; bh=5y2RrcCWt6qO+GV2ka4GPYQ5sZR/6Txvu1d2oiwqgw0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=t7xYg6hgVKzJDUQIBeb4tplYEnEWvBSCSWwIxF6VreiVAra1lRBteubsYJ0iBrnBF k6r2ieF4gyEqpqHZ/gCnqcpo6Fj2t6vP5VYShq32VqSvGtczJ4ozbAdN+bPfhw5ZL7 GFyWR44wXSdWhz2P9EtqeXiXRGPkF70xM8JucVgcYPlL5OvxApdgoa6asmtE9oGbN3 t1FB7H5bHv/WJZMII6KxIE8xSIiO4JsWvi0NMsOYA5iXj5B9Ti8VaFVT9GKaA9qEGx SggQiHdcAVD4X2Rx7qZlXpcyt7BIwtidPgxFR1YyiuDt0Y+C0vyhIcBq3WO+N+zLQt J25XtUAX3lROg== X-Nifty-SrcIP: [153.142.97.92] From: Masahiro Yamada To: u-boot@lists.denx.de Date: Tue, 19 Jun 2018 16:11:45 +0900 Message-Id: <1529392307-26656-5-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1529392307-26656-1-git-send-email-yamada.masahiro@socionext.com> References: <1529392307-26656-1-git-send-email-yamada.masahiro@socionext.com> Subject: [U-Boot] [PATCH 4/6] serial: uniphier: set clock rate without clock-frequency property X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" In Linux, the clock rate of the UART is given by the clock driver. If you try to follow that in U-Boot, you would end up with adding more u-boot,dm-pre-reloc properties, and also the clock driver would be too big for SPL, which is used for UniPhier ARMv7 platform. The current solution is to add 'clock-frequency' property to the UART nodes, but it does not exist in the DT files in Linux. I do not want to let DT diverge for U-Boot. Check the SoC compatible and set the clock rate according to it. This will be helpful to sync DT between Linux and U-Boot. Signed-off-by: Masahiro Yamada --- drivers/serial/serial_uniphier.c | 41 +++++++++++++++++++++++++++++++++++++--- 1 file changed, 38 insertions(+), 3 deletions(-) diff --git a/drivers/serial/serial_uniphier.c b/drivers/serial/serial_uniphier.c index b06fc00..c7f46e5 100644 --- a/drivers/serial/serial_uniphier.c +++ b/drivers/serial/serial_uniphier.c @@ -7,6 +7,7 @@ #include #include +#include #include #include #include @@ -87,11 +88,34 @@ static int uniphier_serial_pending(struct udevice *dev, bool input) return !(readl(&port->lsr) & UART_LSR_THRE); } +/* + * SPL does not have enough memory footprint for the clock driver. + * Hardcode clock frequency for each SoC. + */ +struct uniphier_serial_clk_data { + const char *compatible; + unsigned int clk_rate; +}; + +static const struct uniphier_serial_clk_data uniphier_serial_clk_data[] = { + { .compatible = "socionext,uniphier-ld4", .clk_rate = 36864000 }, + { .compatible = "socionext,uniphier-pro4", .clk_rate = 73728000 }, + { .compatible = "socionext,uniphier-sld8", .clk_rate = 80000000 }, + { .compatible = "socionext,uniphier-pro5", .clk_rate = 73728000 }, + { .compatible = "socionext,uniphier-pxs2", .clk_rate = 88888888 }, + { .compatible = "socionext,uniphier-ld6b", .clk_rate = 88888888 }, + { .compatible = "socionext,uniphier-ld11", .clk_rate = 58823529 }, + { .compatible = "socionext,uniphier-ld20", .clk_rate = 58823529 }, + { .compatible = "socionext,uniphier-pxs3", .clk_rate = 58823529 }, + { /* sentinel */ }, +}; + static int uniphier_serial_probe(struct udevice *dev) { - DECLARE_GLOBAL_DATA_PTR; struct uniphier_serial_priv *priv = dev_get_priv(dev); struct uniphier_serial __iomem *port; + const struct uniphier_serial_clk_data *clk_data; + ofnode root_node; fdt_addr_t base; u32 tmp; @@ -105,8 +129,19 @@ static int uniphier_serial_probe(struct udevice *dev) priv->membase = port; - priv->uartclk = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), - "clock-frequency", 0); + root_node = ofnode_path("/"); + clk_data = uniphier_serial_clk_data; + while (clk_data->compatible) { + if (ofnode_device_is_compatible(root_node, + clk_data->compatible)) + break; + clk_data++; + } + + if (WARN_ON(!clk_data->compatible)) + return -ENOTSUPP; + + priv->uartclk = clk_data->clk_rate; tmp = readl(&port->lcr_mcr); tmp &= ~LCR_MASK;